ISCUG 2012 Slated for April 9-10 in Bangalore

Keynote Presentation by Tor Jeremiassen, Texas Instruments

WHO: The Indian SystemC User Group (ISCUG) conference will take place in Bangalore on April 9-10, 2012 in affiliation with Accellera Systems Initiative, OCP-IP, IEEE and the India Semiconductor Association. The Indian SystemC User's Group organization aims to accelerate the adoption of SystemC as the open source standard for Electronics System Level (ESL) designs.

WHAT/WHEN: ISCUG 2012, Monday, April 9 and Tuesday, April 10.

Day one of this event provides a platform for SystemC beginners, SystemC experts, ESL managers and ESL vendors to share their knowledge, experiences and best practices about SystemC usage. The event is designed on the pattern of similar events happening worldwide including North America (NASCUG), Europe (ESCUG) and Japan (SystemC Day Japan). There will be active discussion about next-generation design and verification methodologies for semiconductors and embedded software.

Day two of this event provides two in-depth tutorials. The morning tutorial, "SystemC and TLM-2.0 Introductory Tutorial," will introduce the main features of the SystemC class library and show how it can be used to model hardware structure, concurrency and time. It will also describe the main features of the TLM-2.0 standard and explain how TLM-2.0 can be used to achieve both speed and interoperability between the transaction-level models used to build a virtual platform. The afternoon tutorial, "The New SystemC Standard - IEEE 1666-2011," will focus on the IEEE 1666 Standard SystemC Language Reference Manual, published early in 2012, which combines SystemC and TLM-2.into a single standard. The tutorial will teach the new features of SystemC and TLM-2.0 in full. In addition, the tutorial will provide an introduction to the forthcoming draft Configuration Standard which targets the configuration of SystemC models.


8:30am - 9:30am

9:30am - 9:40am
Opening Remarks

9:40am - 10:30am
Keynote Speech
Tor Jeremiassen, Simulation and Modeling CTO, Texas Instruments

10:30am - 11:00am
SOC Virtual Prototyping: An Approach towards a Fast System-On-Chip Solution
Mamta Chalana, ST Microelectronics

11:00am - 11:15am
Tea Break

11:15am - 11:45am
Design and Implementation Techniques for Improving Simulation Speed of SystemC Models
Praveen Kumar Kondugari, Aravinda Thimmapuram, Intel

11:45am - 12:15pm
Benefits of Adopting SystemC in TI SoC Verification Process
Nizamudheen Ahmed, Texas Instruments

12:15pm - 1:15pm
System Solutions to Address Today's System Challenges with a Deep Dive on USB 2.0 EHCI TLM Development using Cadence VSP Tools
Praveen Wadikar, Cadence

1:15pm - 2:00pm
Lunch Break

2:00pm - 2:30pm
OCP TLM Kit practical implementation of TLM 2.0
Prashant Karandikar, OCP-IP

2:30pm - 3:00pm
TLM Convenience Socket
Parvinder Pal Singh, Girish Verma, CircuitSutra

3:00pm - 3:30pm
Designing, Verifying and Building an Advanced L2 Cache Subsystem using SystemC
Dave Apte, Forte Design Systems; Thomas D. Tessier, Paneve

3:30pm - 3:45pm
Tea Break

3:45pm - 4:15pm
UML-based Validation for Transaction-level Models
Vaibhav Jain, Anshul Kumar, IIT, Delhi

4:15pm - 4:45pm
Getting Started with SystemC UVM
Puneet Goel, Coverify

4:45pm - 5:15pm
Introducing UVM Connect
Dennis Brophy, Mentor Graphics

5:15pm - 5:45pm
TBD (Sponsor Presentation)

5:45pm - 6:00pm


8:30am - 9:30am

9:30am - 11:00am
Tutorial 1: SystemC and TLM-2.0 Introductory Tutorial

11:00am - 11:20am
Tea Break

11:20am - 1:00pm
Tutorial 1: SystemC and TLM-2.0 Introductory Tutorial (Continued)

1:00pm - 2:00pm
Lunch Break

2:00pm - 3:30pm
Tutorial 2: The New SystemC Standard - IEEE 1666-2011

3:30pm - 3:45pm
Tea Break

3:45pm - 5:45pm
Tutorial 2: The New SystemC Standard - IEEE 1666-2011 (Continued)

5:45pm - 6:00pm

WHERE: Hotel Taj Vivanta, 41/3, MG Road, Bangalore. For details:

REGISTRATION: Register today at:
Early Bird Discount extended to March 31, 2012

ACCELLERA SYSTEMS INITIATIVE GLOBAL EVENT SPONSORS: ARM, Cadence, CircuitSutra Technologies, Forte Design Systems, Mentor Graphics, Synopsys

ISCUG SPONSORS: Cadence, CircuitSutra Technologies, Doulos, Forte Design Systems, Mentor Graphics, OCP-IP

Accellera Systems Initiative is an independent, not-for-profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development, and as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit For membership information, please email

Accellera Systems Initiative, SystemC, and UVM are trademarks of Accellera Systems Initiative Inc. All other trademarks and trade names are the property of their respective owners.