Accellera Day India 2020

Accellera Day India 2020

December 2&3, 2020
9:00am – 1:00pm IST

Virtual Event

Registration will open soon - please check back!

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Welcome from the General Chair

Sanjay MuchiniA note from Sanjay Muchini, Accellera Day India 2020 General Chair

I take great pleasure in inviting you to Accellera Day India – Virtual Edition, scheduled on December 2nd and 3rd, 2020!

Accellera Day India 2020 technical program, sponsored by Accellera Systems Initiative, provides multiple opportunities to interact with industry and academia domain experts delivering keynote speeches and tutorials. It is truly a privilege to present the Accellera Day 2020 India event, virtual this time, that will provide an excellent platform to survey and learn the latest in design and verification technologies, methodologies, and tools from the best in the industry.

This year we have tailored Accellera Day India as an in-depth two half-day virtual technical program on December 2nd & 3rd. The conference has keynotes from industry & academia, Accellera working group updates, and tutorials. The technical conference targets latest trends and challenges on Automotive domain, Functional Safety & Security, RISC-V architecture verification, UVM standards, Portable Stimulus standard, and Formal Verification. Tutorials will focus on deep technical concepts and challenges and solutions, relevant to most of the engineers working in the verification domain. The examples will help engineers related to and solve some of the challenges they are facing in their day-to-day activities.

The event is a must attend for industry leaders, engineering managers, system architects, verification experts, SoC integrators, chip designers, EDA vendors, CAD and IP developers, emulation and post-Si validation engineers, VIP developers, and firmware engineers working on the latest cutting edge semiconductor products.

For 2020, our focus remains unchanged: to offer a compelling event where technical experts active in system-level design and verification can interact, share best practices, and learn the latest design and verification methodologies, language, and standards to create competitive advantage to their organizations.

The India steering committee wishes you a warm welcome and an enjoyable Accellera Day India 2020!

Sanjay Muchini
Accellera Day India 2020 General Chair

 

Agenda

Start Time End Time Day 1
December 2, 2020
Day 2
December 3, 2020
9:00am 9:10am Welcome & Overview Welcome & Overview
9:10am 9:40am RISC V Architecture and Verification Challenges
Prof. V. Kamakoti, IIT Chennai
Safe and Secure Mobility: The "Safe" ? Road Ahead
Yogesh Mittal, NXP Semiconductors
9:40am 9:55am Accellera Working Group Update | IP Security Accellera Working Group Update | Functional Safety
9:55am 10:00am Break Break
10:00am 11:20am Formal Verification, The Designer's Armor
Achutha Kiran Kumar, Intel
Portable Stimulus: What's Coming in 2.0 and What It Means to You
Tom Fitzpatrick, Siemens EDA
Leigh Brady, Breker
Matan Vax, Cadence
Karthick Gururaj, Vayavya Labs
Hillel Miller and Gaurav Chugh, Synopsys
11:20am 11:30am Break Break
11:30am 12:50pm USB4: Protocol and Verification Challenges
Neelabh Singh, Cadence
Pandithurai Sangaiyah, Intel
Tutorial – UVM for Advanced Users
Ashok Chandran, ADI
12:50pm 1:00pm Closing Remarks Closing Remarks

Sponsorship Opportunities

For more information about becoming a sponsor contact Abhijeet Khopkar, Sponsorship Chair: This email address is being protected from spambots. You need JavaScript enabled to view it.

Sponsorship Type Cost (INR) Benefits
Gold 1,50,000 • Your company logo displayed in the backdrop during Tech Talks/Tutorials/Breaks as Gold sponsor
• Your company logo displayed on the Accellera Day India web page as Gold sponsor
• Your company logo sent out in all mailers as Gold sponsor
• Your company mentioned in the opening session presentation slides
• 10 free registrations
Registration 75,000 • Your company logo and sponsorship status recognized on the Registration information page on the Accellera Day India web page
• Company recognition on all conference email distributions that promote registration
• Your company mentioned in the opening session presentation slides
• 5 free registrations
Tutorial 75,000 • Your company logo displayed in the background during Tutorials
• Your company logo displayed on the Accellera Day India website
• Your company mentioned in the opening session presentation slides
• Includes 5 free registrations
Coffee Break 37,000 • Your logo and sponsorship status recognized during 2 Attendee Breaks
• Your logo displayed in background during Break sessions
• Your company mentioned in the opening session presentation slides
• Your logo and sponsorship status recognized on the Accellera Day India website
• Includes 2 free registrations

 

Keynote Speakers

Day 1: Prof. Kamakoti V, IIT Chennai

Dr. V. KamakotiKamakoti Veezhinathan is a Professor of Computer Science & Engineering, IIT Madras. He was also the Chairman of the Artificial Intelligence Task Force constituted by the Ministry of Commerce and Industry, Government of India. He specializes in the area of Computer Architecture, Information Security and VLSI Design. He also heads the Microprocessor Development Program and the Information Security Education and Awareness Program funded by the Ministry of Electronics and Information Technology, Government of India.

Dr. V. Kamakoti received the M.S. degree and the Ph.D. degree in computer science and engineering from IIT Madras, Chennai, India. He is currently a Professor with the Department of Computer Science and Engineering and Associate Dean at ICSR,IIT Madras. He has more than 15 years of experience in computer systems development and specializes in the area of computer architecture, CAD for VLSI, and high-performance computing. Dr. Kamakoti took SHAKTI processor initiative which aim to break the barrier between Academia and Industry by providing open-source Processor and SoC designs. He has authored a number of research papers that have been published in various international journals and in the PROCEEDINGS of many scientific conferences. Dr. Kamakoti also has interest in writing literature and has published Ganiporiyum Adipadiyum, a book in Tamil released in 1992. Dr. Kamakoti received DRDO Academic Excellence Award instituted by DRDO in recognition of the contribution from Academicians to various programs of DRDO. Recently, Dr. Kamakoti was awarded Techno Visionary Award, which is a lifetime achievement award given to an Indian academician, who made significant contributions to the field of Electronics and Semiconductor through research and development.

Day 2: Yogesh Mittal, NXP Semiconductors

Yogesh MittalYogesh is a Sr. Director at NXP Semiconductors. He is a Global Functional Verification Leader with 23+ years of experience in the field of SoC/ASIC Architecture, Design verification, Emulation and Post Silicon Validation of IPs/SoCs/FPGA/ASSPs meant for Automotive/Industrial Microcontrollers and Networking Systems. High end Safe and Secure ADAS-Radar & Vision processors for Autonomous driving with ISO26262 based functional safety, Infotainment processors etc. have been driving evolution in Automotive industry.

Yogesh built and lead geographically diverse teams and scaled them to create a centre of excellence in IP, Front End Design, Verification, Emulation and Post Silicon Validation. He focused strongly on initiatives and value additions to product methodologies and execution excellence. He is also in collaboration with SOC leaders from other geography/multiple sites to establish Industry best practices and methodologies.

 

Tutorial Speakers

M, Achutha KiranKumar, Intel

Achutha KiranKumarKiranKumar is a Senior Principal Engineer leading Formal Verification Central Tech Office under the IPG Group, driving formal verification across various IPs and SOCs across Intel. Kiran graduated from Indian Institute of Sciences, Bangalore in 2003 and has been working with Intel since then. He started his career as an RTL Design Engineer in the Xeon group and donned various hats to learn Schematic design, Physical design and Verification lead before starting the Formal verification group for Graphics. He drives formal verification across Intel now and is responsible for the embrace of FV across various design houses in Intel. He own a patent, co-authored a book on Formal verification, authored more than 80 internal and external papers, and received more than 12 best paper awards.

His motto is to make formal verification mainstream in the design cycle, and he owes his success to his strong team of FV enthusiasts and experts.

Neelabh SinghNeelabh Singh, Cadence Design Systems

Neelabh Singh is the Product Engineering Architect in the Verification IP (VIP) group at Cadence Design Systems.

He has been associated with the VIP domain for 20 years on different protocols.

In recent years his focus has been on USB4 and its various verification aspects.

Pandithurai Sangaiyah, Intel

Pandithurai SangaiyahPandithurai Sangaiyah heads the IP team spanning across design, verification, product development engineering, integration and post silicon validation for a differentiated IP product from Intel India. He comes with 20 years of experience in the Semiconductor Industry.

He has authored multiple papers in internal and external conferences in the fields of low power DV challenges in DDR systems, beating sub-system performance with UVM framework, and FW shift-left validation using UVM framework, to count a few.

Ashok Chandran, Analog Devices

Ashok ChandranAshok Chandran is a Design Verification Engineering Director in the Wireless Communications Business Unit at Analog Devices. He leads a team with focus on Design Verification, Emulation and Prototyping. In this role, he sets technology direction & methodology for verification of multiple Wireless Communication SoCs from Analog Devices. He has also led successful Pre-Silicon verification of multiple DSP SoC projects for Analog Devices in the past.

He has interests in virtual prototyping, modeling and system verification with focus on domains of Signal Processing, Communications & Algorithms. Ashok received his Bachelors in Electronics and Communication from the College of Engineering, Trivandrum.

Roy Vincent, Analog Devices

Roy VincentRoy Vincent completed his B-Tech in electronics and communication from University of Calicut, Kerala and M-Tech in microelectronics from BITS. He is associated with Analog Devices since 2011. His main area of interest is digital electronics.

He has been working in the verification domain and has been involved in block and system level verification of DSPs and transceivers and building scalable testbenches. UVM, formal DV, systemC, emulation are his main fields of expertise.

 

Organizing Committee

  • Sanjay Muchini, Qualcomm: General Chair
  • Pradeep Salla, Mentor, a Siemens Business: Vice Chair & Finance Chair
  • Lokesh Babu Pundreeka, Cadence: Program Chair
  • Karthikeyan Subramanian, Qualcomm: Tutorial Co-Chair
  • Abhijeet Khopkar, Synopsys: Tutorial Co-Chair & Sponsorship Chair
  • Veeresh Shetty, Mentor, a Siemens Business: Marketing, Platform & Registration Chair
  • Samuel Dorairaj, Intel: Publicity & Promotions Chair