UVM-AMS Proposed Working Group

The Accellera Board of Directors recently approved the formation of a Proposed Working Group (PWG) to focus on the standardization of analog/mixed signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. There have been various proposals presented at recent DVCon events addressing the need for AMS extensions for UVM to enrich and improve the verification of analog/mixed-signal products and applications. Most of these proposals offer similar capabilities, but often use different implementations to resolve existing constraints enforced by UVM or to address limitations caused by mixing languages such as SystemVerilog and Verilog-AMS. The objective of the PWG is to explore the need for standardized UVM mixed-signal extensions and offer a unified approach for mixed-signal verification.

The first UVM-AMS PWG meeting will be held Wednesday, May 22 at NXP Semiconductors, Schatzbogen 7, 81829 Munich, Germany. The meeting is planned from 10am to 4pm CEST and will cover presentations on industry best practices, discuss scope and requirements, and explore directions for standardization. For more information on the UVM-AMS PWG, visit here.

Join us at DAC for our Luncheon and Panel of Industry Experts Addressing IP Security Assurance Issues

Monday, June 3
Noon-1:30pm
Room N246, Las Vegas Convention Center

We invite you to join us at DAC for a brief update on Accellera activities from our Chair Lu Dai, followed by an informative and thought-provoking panel addressing IP security issues. Security is as important to electronic systems as functionality is. This statement is bold, but it is reality. While the need is obvious in mission-critical applications such as automotive, communications, defense, industrial, and medical, no one wants to see their cell phone compromised or have their robotic lawnmower run amok. Therefore, security principles must exist in all levels of these systems, must be addressed at all phases of product development, and must be sustained throughout the product lifecycle. The Accellera-sponsored luncheon is free to DAC attendees, but registration is required. Find out more and register >

New Technical Tutorial Available: "Gain Valuable Insight into — and Make the Most Out of — the Changes and Features that Are Part of the New IEEE 1800.2 Standard for UVM"

Delivered at DVCon U.S. 2019 by Cliff Cummings of Sunburst Design, this tutorial dives into the changes and features that are part of the new IEEE 1800.2 standard for UVM. Cliff offers clarification and guidelines for UVM messaging and verbosities. He also explains the origins of the two different techniques to define UVM transactions and execute sequences, including the advantages and disadvantages of each. With this knowledge, viewers have a greater understanding of all publicly available UVM examples. Viewers also benefit from Cliff’s favorite UVM tips and tricks. View tutorial >