Working Groups

The mission of Accellera Systems Initiative is to deliver standards that lower the cost of designing commercial IC and EDA products and embedded system solutions, as well as increase the productivity of designers worldwide. The Technical Committee is where this mission is realized, and through its dedicated work, EDA and IP standard are developed that enable and promote technology innovation.

The Board of Directors of Accellera Systems Initiative established the Technical Committee (TC) to develop, update and extend hardware design language (HDL) and intellectual property (IP) standards. The TC is comprised of working groups that focus on the various standards under development, and report to the TC Chair. In addition, Accellera supports activities of certain IEEE working groups and cooperates with other standards groups within the EDA industry.

Membership at the Corporate or Associate level is required to join a Working Group or have a vote on specifications and standards. Learn more about the different levels of membership.

Active Working Groups

Working Group Chair
IP-XACT Erwin de Kock, NXP
IP Security Assurance (IPSA) Brent Sherman, Intel
Multi-Language (ML) Warren Stapleton, AMD
Portable Stimulus Faris Khundakjie, Intel
SystemC  
SystemC Analog/Mixed-Signal (AMS) Martin Barnasconi, NXP
SystemC Configuration, Control and Inspection (CCI) Trevor Wieman, Intel
SystemC Language Philipp Hartmann, Intel
SystemC Datatypes position currently vacant
SystemC Synthesis Andres Takach, Mentor, a Siemens Business
SystemC Transaction-level Modeling (TLM) Bart Vanthournout, Synopsys
SystemC Verification Stephan Gerth, Bosch-Sensortec
SystemVerilog-AMS (Analog Mixed-Signal) Scott Little, Maxim
Universal Verification Methodology (UVM) Justin Refice, NVIDIA

Dormant Working Groups