Index of /vug_bbs/SSI_LIBRARY
Name Last modified Size Description
![[DIR]](/icons/back.gif)
Parent Directory 22-Dec-2003 10:19 -
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DID_files/ 22-Dec-2003 10:19 -
STD_PACK/ 22-Dec-2003 10:19 -
STD_WAVES/ 27-Mar-1997 13:43 -
TTL/ 27-Mar-1997 13:43 -
The files contained in this release of TTL VHDL models are contained in four
directories. Those directories are:
DID_files - Deliverable files specified in section 10.3 of the VHDL DID
(DI-EGDS-80811)
STD_PACK - Logic package common to all 19 models
STD_WAVES - WAVES packages common to all models
TTL - the models themselves
The contents of the directories are listed as follows:
DID_files:
vhdl_files.txt -- names of all files of the data item
vhdl_overview.txt -- high-level prose overview of the data item
vhdl_analysis.txt -- specification of order of analysis
vhdl_leaves.txt -- list of modules selected from the Government
list of leaf level modules
vhdl_revisions.txt -- list of modules which are revisions of
modules previously accepted by the Government
vhdl_originals.txt -- list of modules which originate with this
VHDL delivery
test_benches.txt -- list which associates VHDL modules with
their corresponding test benches
STD_PACK:
BASICDEFS_.vhd -- definition of basic logic system
BASICDEFS.vhd -- definition of basic logic functions
TIME_FUNC.vhd -- timing violation functions
STD_WAVES/STANDARD: (Standard WAVES packages)
waves_standard_.vhd
waves_standard.vhd
waves_objects_.vhd
waves_objects.vhd
waves_interface_.vhd
waves_interface.vhd
waves_port_.vhd
waves_port.vhd
STD_WAVES/LOCAL: (Environment-specific WAVES packages)
waves_events_.vhd
waves_events.vhd
waves_frames_.vhd
waves_frames.vhd
waves_utilities_.vhd
waves_utilities.vhd
TTL/SN5438:
SN5438_SIMFLAG_.vhd -- user-selectable options declaration file
SN5438_SIMFLAG.vhd -- SIMFLAG package body
SN5438.tim.vhd -- timing module
SN5438_.vhd -- entity declaration for the model
SN5438.vhd -- architecture declaration for the model
waves_device_SN5438_.vhd -- package which describes the test pins
waves_device_SN5438.vhd -- waves_device package body
wgenerator_SN5438_.vhd -- WAVES test program package
wgenerator_SN5438.vhd -- WAVES test program package body
SN5438_TB_.vhd -- test bench entity
SN5438_TB.vhd -- test bench architecture
TTL/SN54368:
SN54368_SIMFLAG_.vhd
SN54368_SIMFLAG.vhd
SN54368.tim.vhd
SN54368_.vhd
SN54368.vhd
waves_device_SN54368_.vhd
waves_device_SN54368.vhd
wgenerator_SN54368_.vhd
wgenerator_SN54368.vhd
SN54368_TB_.vhd
SN54368_TB.vhd
TTL/SN54LS00:
SN54LS00_SIMFLAG_.vhd
SN54LS00_SIMFLAG.vhd
SN54LS00.tim.vhd
SN54LS00_.vhd
SN54LS00.vhd
waves_device_SN54LS00_.vhd
waves_device_SN54LS00.vhd
wgenerator_SN54LS00_.vhd
wgenerator_SN54LS00.vhd
SN54LS00_TB_.vhd
SN54LS00_TB.vhd
TTL/SN54LS04:
SN54LS04_SIMFLAG_.vhd
SN54LS04_SIMFLAG.vhd
SN54LS04.tim.vhd
SN54LS04_.vhd
SN54LS04.vhd
waves_device_SN54LS04_.vhd
waves_device_SN54LS04.vhd
wgenerator_SN54LS04_.vhd
wgenerator_SN54LS04.vhd
SN54LS04_TB_.vhd
SN54LS04_TB.vhd
TTL/SN54LS109:
SN54LS109_SIMFLAG_.vhd
SN54LS109_SIMFLAG.vhd
SN54LS109.tim.vhd
SN54LS109_.vhd
SN54LS109.vhd
waves_device_SN54LS109_.vhd
waves_device_SN54LS109.vhd
wgenerator_SN54LS109_.vhd
wgenerator_SN54LS109.vhd
SN54LS109_TB_.vhd
SN54LS109_TB.vhd
TTL/SN54LS112:
SN54LS112_SIMFLAG_.vhd
SN54LS112_SIMFLAG.vhd
SN54LS112.tim.vhd
SN54LS112_.vhd
SN54LS112.vhd
waves_device_SN54LS112_.vhd
waves_device_SN54LS112.vhd
wgenerator_SN54LS112_.vhd
wgenerator_SN54LS112.vhd
SN54LS112_TB_.vhd
SN54LS112_TB.vhd
TTL/SN54LS161:
SN54LS161_SIMFLAG_.vhd
SN54LS161_SIMFLAG.vhd
SN54LS161.tim.vhd
SN54LS161_.vhd
SN54LS161.vhd
waves_device_SN54LS161_.vhd
waves_device_SN54LS161.vhd
wgenerator_SN54LS161_.vhd
wgenerator_SN54LS161.vhd
SN54LS161_TB_.vhd
SN54LS161_TB.vhd
TTL/SN54S00:
SN54S00_SIMFLAG_.vhd
SN54S00_SIMFLAG.vhd
SN54S00.tim.vhd
SN54S00_.vhd
SN54S00.vhd
waves_device_SN54S00_.vhd
waves_device_SN54S00.vhd
wgenerator_SN54S00_.vhd
wgenerator_SN54S00.vhd
SN54S00_TB_.vhd
SN54S00_TB.vhd
TTL/SN54S02:
SN54S02_SIMFLAG_.vhd
SN54S02_SIMFLAG.vhd
SN54S02.tim.vhd
SN54S02_.vhd
SN54S02.vhd
waves_device_SN54S02_.vhd
waves_device_SN54S02.vhd
wgenerator_SN54S02_.vhd
wgenerator_SN54S02.vhd
SN54S02_TB_.vhd
SN54S02_TB.vhd
TTL/SN54S04:
SN54S04_SIMFLAG_.vhd
SN54S04_SIMFLAG.vhd
SN54S04.tim.vhd
SN54S04_.vhd
SN54S04.vhd
waves_device_SN54S04_.vhd
waves_device_SN54S04.vhd
wgenerator_SN54S04_.vhd
wgenerator_SN54S04.vhd
SN54S04_TB_.vhd
SN54S04_TB.vhd
TTL/SN54S08:
SN54S08_SIMFLAG_.vhd
SN54S08_SIMFLAG.vhd
SN54S08.tim.vhd
SN54S08_.vhd
SN54S08.vhd
waves_device_SN54S08_.vhd
waves_device_SN54S08.vhd
wgenerator_SN54S08_.vhd
wgenerator_SN54S08.vhd
SN54S08_TB_.vhd
SN54S08_TB.vhd
TTL/SN54S11:
SN54S11_SIMFLAG_.vhd
SN54S11_SIMFLAG.vhd
SN54S11.tim.vhd
SN54S11_.vhd
SN54S11.vhd
waves_device_SN54S11_.vhd
waves_device_SN54S11.vhd
wgenerator_SN54S11_.vhd
wgenerator_SN54S11.vhd
SN54S11_TB_.vhd
SN54S11_TB.vhd
TTL/SN54S112:
SN54S112_SIMFLAG_.vhd
SN54S112_SIMFLAG.vhd
SN54S112.tim.vhd
SN54S112_.vhd
SN54S112.vhd
waves_device_SN54S112_.vhd
waves_device_SN54S112.vhd
wgenerator_SN54S112_.vhd
wgenerator_SN54S112.vhd
SN54S112_TB_.vhd
SN54S112_TB.vhd
TTL/SN54S138:
SN54S138_SIMFLAG_.vhd
SN54S138_SIMFLAG.vhd
SN54S138.tim.vhd
SN54S138_.vhd
SN54S138.vhd
waves_device_SN54S138_.vhd
waves_device_SN54S138.vhd
wgenerator_SN54S138_.vhd
wgenerator_SN54S138.vhd
SN54S138_TB_.vhd
SN54S138_TB.vhd
TTL/SN54S140:
SN54S140_SIMFLAG_.vhd
SN54S140_SIMFLAG.vhd
SN54S140.tim.vhd
SN54S140_.vhd
SN54S140.vhd
waves_device_SN54S140_.vhd
waves_device_SN54S140.vhd
wgenerator_SN54S140_.vhd
wgenerator_SN54S140.vhd
SN54S140_TB_.vhd
SN54S140_TB.vhd
TTL/SN54S175:
SN54S175_SIMFLAG_.vhd
SN54S175_SIMFLAG.vhd
SN54S175.tim.vhd
SN54S175_.vhd
SN54S175.vhd
waves_device_SN54S175_.vhd
waves_device_SN54S175.vhd
wgenerator_SN54S175_.vhd
wgenerator_SN54S175.vhd
SN54S175_TB_.vhd
SN54S175_TB.vhd
TTL/SN54S251:
SN54S251_SIMFLAG_.vhd
SN54S251_SIMFLAG.vhd
SN54S251.tim.vhd
SN54S251_.vhd
SN54S251.vhd
waves_device_SN54S251_.vhd
waves_device_SN54S251.vhd
wgenerator_SN54S251_.vhd
wgenerator_SN54S251.vhd
SN54S251_TB_.vhd
SN54S251_TB.vhd
TTL/SN54S280:
SN54S280_SIMFLAG_.vhd
SN54S280_SIMFLAG.vhd
SN54S280.tim.vhd
SN54S280_.vhd
SN54S280.vhd
waves_device_SN54S280_.vhd
waves_device_SN54S280.vhd
wgenerator_SN54S280_.vhd
wgenerator_SN54S280.vhd
SN54S280_TB_.vhd
SN54S280_TB.vhd
TTL/SN54S86:
SN54S86_SIMFLAG_.vhd
SN54S86_SIMFLAG.vhd
SN54S86.tim.vhd
SN54S86_.vhd
SN54S86.vhd
waves_device_SN54S86_.vhd
waves_device_SN54S86.vhd
wgenerator_SN54S86_.vhd
wgenerator_SN54S86.vhd
SN54S86_TB_.vhd
SN54S86_TB.vhd
-----------------------------------------------------------------------
NOTES:
1) Please direct any questions and comments pertaining to the
subset to:
Gordon Newell (601)325-2240 newell@itd.msstate.edu
Steve Turner (601)325-2240 turner@itd.msstate.edu
Scott Calhoun (601)325-2240 jscott@itd.msstate.edu
2) These models are intended to be written using the EIA Commercial
Component Specification as a guideline rather than a spec. The
EIA Commercial Component Specification and its accompanying
documents (Blank Detailed Specification and BASICDEFS) are currently
in a non-finalized state. Therefore, some interpretation to
their meaning and direction was taken by the model writers.
It is intended to make this subset fully compliant to the EIA
specifications at such a time when these specs are solidified.
3) These models have been exercised on both the Intermetrics 2.1 tool
platform on a Sun 3/60 and the Zycad 2.0a tool platform on a Sun 4/60,
and found to run correctly. Please report any problems with running the
subset on any additional VHDL platforms to the persons listed above.
4) The model subset utilizes the Hughes developed approach to
implementing environmental timing into the models. A procedure
called "get_timing" resides within the timing module for each
model ({model}.tim.vhd). This procedure is called during
elaboration and is used to determine the propagation delays
which will be used for that particular simulation run. The choice
of propagation delays is determined by user selectable
deferred constants that reside in the simulation flags package
body ({model}_SIMFLAG.vhd). These simulation flags allow the user
to select the environmental and operating conditions that he
wishes to operate the model under.
5) The model subset does not at this time support the ANNOTATED option
in the simulation flags package. If the ANNOTATED option is
selected, the model will print an error message, and then
simulate using the GENERIC timing data.
6) The implementation of uninitialized states ('U') in these models
is as follows:
An output is set to 'U' if both of the following conditions are true:
1. Input conditions are such that an unknown output ('X') would be
asserted.
2. Any input has a value of 'U'.
7) The Waveform And Vector Exchange Specification (WAVES) is a standard
for describing test vectors. The WAVES code is contained in a set of
standard packages, and a set of packages specific to the model being tested.
The WAVES packages are distributed for the purposes of evaluating the
Waveform And Vector Exchange Specification (WAVES) proposal presented
to the IEEE by the WAVES Analysis Group. The WAVES code may not be used
for commercial purposes and may not be redistributed without permission
of the Chairman of the WAVES Analysis Group, Mr. Robert Hillman.