VHDLSynth (1076.3) Home page

The VHDL Synthesis working group (IEEE 1076.3) is working on standardizing synthesizable VHDL code. We have one package which uses "BIT" logic and another which is "STD_LOGIC" (IEEE 1164-1993) based.  

This specification has been included into the vhdl-200x-ft (VHDL 200X Fast track) specification, currently schedules for release at the end of 2004. The Numeric Package Proposals for the work being done on this specification.

This standard can be ordered from the IEEE. Look at the IEEE CAD Standards catalog to see the price list. For ordering information look at the IEEE Draft standards services. Due to restrictictions imposed by the IEEE, we can not post the source code to our web page.

Some of the more important documents available are:

• Our e-mail reflector is now inactive. You can join the vhdl-200x-ft e-mail reflector to join in on our discussions.
• To view our e-mail logs, just click here. (for the pilot group they are here)
• Get the updated version of MVP a VHDL pretty printer, (updated for USA A size paper and associated font bugs). (Updated 5/22/00)
  • MVPX is a PC version of this MVP.
• ESA VHDL Modeling Guidelines and activities report.
• VHDL random number generator documentation and code.

Links:

• IEEE std_logic_1164 working group
• VHDL Synthesis Interoperability Working Group 1076.6
• Verilog Synthesis Interoperability Working group 1364.1
• See our links page for a list of other IEEE specs and VHDL web sites.

About the eda.org machine

There are many groups with repositories and email exploders on the VHDL International Users' Forum (VIUF) Internet Services (VIIS) System. For more information about the VIIS supported features and access mechanisms (such as email, Internet or public dial-up), click here.

Group Sysop: