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Sections 1 and 2 specify the Verilog Procedural Interface (VPI) for the Verilog-AMS HDL. This section describes how the VPI routines are used and Section 2 defines each of the routines in alphabetical order.
1.1 The VPI interface
The VPI interface provides routines which allow Verilog-AMS product users to access information contained in a Verilog-AMS design and allow facilities to interact dynamically with a software product. Applications of the VPI interface can include delay calculators and annotators, connecting a Verilog-AMS simulator with other simulation and CAE systems, and customized debugging tasks.
The functions of the VPI interface can be grouped into two main areas:
· Dynamic software product interaction using VPI callbacks
· Access to Verilog-AMS HDL objects and simulation specific objects
1.1.1 VPI callbacks
Dynamic software product interaction shall be accomplished with a registered callback mechanism. VPI callbacks shall allow a user to request a Verilog-AMS HDL software product, such as a logic simulator, call a user-defined application when a specific activity occurs. For example, the user can request the user application my_monitor() be called when a particular net changes value or my_cleanup() be called when the software product execution has completed.
The VPI callback facility shall provide the user with the means to interact dynamically with a software product, detecting the occurrence of value changes, advancement of time, end of simulation, etc. This feature allows applications such as integration with other simulation systems, specialized timing checks, complex debugging features, etc. to be used.
The reasons for providing callbacks can be separated into four categories:
· Simulation event (e.g., a value change on a net or a behavioral statement execution)
· Simulation time (e.g., the end of a time queue or after certain amount of time)
· Simulator action/feature (e.g., the end of compile, end of simulation, restart, or enter interactive mode)
· User-defined system task or function execution
VPI callbacks shall be registered by the user with the functions vpi_register_cb(), vpi_register_systf() and vpi_register_analog_systf(). These routines indicate the specific reason for the callback, the application to be called, and what system and user data shall be passed to the callback application when the callback occurs. A facility is also provided to call the callback functions when a Verilog-AMS HDL product is first invoked. A primary use of this facility shall be for the registration of user-defined system tasks and functions.
1.1.2 VPI access to Verilog-AMS HDL objects and simulation objects
Accessible Verilog-AMS HDL objects and simulation objects and their relationships and properties are described using data model diagrams. These diagrams are presented in 1.5. The data diagrams indicate the routines and constants which are required to access and manipulate objects within an application environment. An associated set of routines to access these objects is defined in Section 2.
The VPI interface also includes a set of utility routines for functions such as handle comparison, file handling, and redirected printing, which are described in 2.12.
VPI routines provide access to objects in an instantiated Verilog-AMS design. An instantiated design is one where each instance of an object is uniquely accessible. For instance, if a module m contains wire w and is instantiated twice as m1 and m2, then m1.w and m2.w are two distinct objects, each with its own set of related objects and properties.
The VPI interface is designed as a simulation interface, with access to both Verilog-AMS HDL objects and specific simulation objects. This simulation interface is different from a hierarchical language interface, which would provide access to HDL information but would not provide information about simulation objects.
1.1.3 Error handling
To determine if an error occurred, the routine vpi_chk_error() shall be provided. The vpi_chk_error() routine shall return a nonzero value if an error occurred in the previously called VPI routine. Callbacks can be set up for when an error occurs as well. The vpi_chk_error() routine can provide detailed information about the error.
1.2 VPI object classifications
VPI objects are classified with data model diagrams. These diagrams provide a graphical representation of those objects within a Verilog-AMS design to which the VPI routines shall provide access. The diagrams shall show the relationships between objects and the properties of each object. Objects with sufficient commonality are placed in groups. Group relationships and properties apply to all the objects in the group.
As an example, the simplified diagram in Figure 121 shows there is a one-to-many relationships from objects of type module to objects of type net and a one-to-one relationship from objects of type net to objects of type module. Objects of type net have properties vpiName, vpiVector, and vpiSize, with the C data types string, Boolean, and integer respectively.
The VPI object data diagrams are presented in 1.5.
1.2.1 Accessing object relationships and properties
The VPI interface defines the C data type of vpiHandle. All objects are manipulated via a vpiHandle variable. Object handles can be accessed from a relationship with another object, or from a hierarchical name, as the following example demonstrates.
Examples:
vpiHandle net;
net = vpi_handle_by_name("top.m1.w1", NULL);
This example call retrieves a handle to wire top.m1.w1 and assigns it to the vpiHandle variable net. The NULL second argument directs the routine to search for the name from the top level of the design.
The VPI interface provides generic functions for tasks, such as traversing relationships and determining property values. One-to-one relationships are traversed with routine vpi_handle().
Examples:
In the following example, the module containing net is derived from a handle to that net:
vpiHandle net, mod;
net = vpi_handle_by_name("top.m1.w1", NULL);
mod = vpi_handle(vpiModule, net);
The call to vpi_handle() in the above example shall return a handle to module top.m1.
Properties of objects shall be derived with routines in the vpi_get family. The routine vpi_get() returns integer and Boolean properties. The routine vpi_get_str() accesses string properties.
Example:
To retrieve a pointer to the full hierarchical name of the object referenced by handle mod, the following call would be made:
char *name = vpi_get_str(vpiFullName, mod);
In the above example, character pointer name shall now point to the string top.m1.
One-to-many relationships are traversed with an iteration mechanism. The routine vpi_iterate() creates an object of type vpiIterator, which is then passed to the routine vpi_scan() to traverse the desired objects.
Examples:
In the following example, each net in module top.m1 is displayed:
vpiHandle itr;
itr = vpi_iterate(vpiNet,mod);
while (net = vpi_scan(itr) )
vpi_printf("\t%s\n", vpi_get_str(vpiFullName, net) );
As the above examples illustrate, the routine naming convention is a vpi prefix with `_' word delimiters (with the exception of callback-related defined values, which use the cb prefix). Macro-defined types and properties have the vpi prefix and they use capitalization for word delimiters.
The routines for traversing Verilog-AMS HDL structures and accessing objects are described in IEEE 1364-1995 Verilog HDL, section 22.
1.2.2 Delays and values
Properties are of type integer, boolean, real or string. Delay and logic value properties, however, are more complex and require specialized routines and associated structures. The routines vpi_get_delays() and vpi_put_delays() use structure pointers, where the structure contains the pertinent information about delays. Similarly, simulation values are also handled with the routines vpi_get_value() and vpi_put_value(), along with an associated set of structures. For analog tasks and functions, vpi_handle_multi() and vpi_put_value() support declaration and assignment of derivatives for the task arguments and function return values.
The routines and C structures for handling delays, derivatives, and logic values are presented in IEEE 1364-1995 Verilog HDL, section 22.
1.3 List of VPI routines by functional category
The VPI routines can be divided into groups based on primary functionality.
· VPI routines for simulation-related callbacks
· VPI routines for system task/function callbacks
· VPI routines for traversing Verilog-AMS HDL hierarchy
· VPI routines for accessing properties of objects
· VPI routines for accessing objects from properties
· VPI routines for delay processing
· VPI routines for logic and strength value processing
· VPI routines for task parameters derivatives processing
· VPI routines for analysis and simulation time processing
· VPI routines for miscellaneous utilities
Table 121 through Table 129 list the VPI routines by major category. IEEE 1364-1995 Verilog HDL, Section 22 defines each of the VPI routines, listed in alphabetical order.
Register a simulation-related callback Remove a simulation-related callback Get information about a simulation-related callback
Table 12-2- VPI routines for system task/function callbacks Register a system task/function callback Get information about a system task/function callback
Table 12-3- VPI routines for analog system task/function callbacks Register a analog system task/function callback Get information about a analog system task/function callback
Table 12-6- VPI routines for accessing objects from properties Obtain a handle for a named object Obtain a handle for an indexed object
Table 12-7- VPI routines for delay processing Retrieve delays or timing limits of an object Write delays or timing limits to an object
1.4 Key to object model diagrams
This clause contains the keys to the symbols used in the object model diagrams. Keys are provided for objects and classes, traversing relationships, and accessing properties.
1.4.1 Diagram key for objects and classes
1.4.2 Diagram key for accessing properties
1.4.3 Diagram key for traversing relationships
1.5 Object data model diagrams
Subclauses 1.5.1 through 1.5.26 contain the data model diagrams which define the accessible objects and groups of objects, along with their relationships and properties.
1.5.1 Module
1.5.2Nature, discipline
1.5.3 Scope, task, function, IO declaration
1.5.4 Ports
1.5.5 Nodes
1.5.6 Branches
1.5.7 Quantities
1.5.8 Nets
1.5.9 Regs
1.5.10 Variables, named event
1.5.11 Memory
1.5.12 Parameter, specparam
1.5.13 Primitive, prim term
1.5.14 UDP
1.5.15 Module path, timing check, intermodule path
1.5.16 Task and function call
1.5.17 Continuous assignment
1.5.18 Simple expressions
1.5.19 Expressions
1.5.20 Contribs
1.5.21 Process, block, statement, event statement
1.5.22 Assignment, delay control, event control, repeat control
1.5.23 While, repeat, wait, for, forever
1.5.24 If, if-else, case
1.5.25 Assign statement, deassign, force, release, disable
1.5.26 Callback, time queue
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