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All Verilog-AMS HDL compiler directives are preceded by the ` character. This character is called accent grave. It is different from the ' character, which is the single quote character. The scope of compiler directives extends from the point where it is processed, across all files processed, to the point where another compiler directive supersedes it or the processing completes.
This section describes the following compiler directives:
`default_discipline
`default_transition
`define
`else
`endif
`ifdef
`include
`resetall
`undef
Those compiler directives defined in IEEE 1364-1995 Verilog HDL are also supported.
11.1 `default_discipline
`default_discipline controls the net_discipline type created for implicit net declarations (see 3.4.6). It can be used only outside of module definitions. It affects all modules which follow the directive, even across source file boundaries. Multiple `default_discipline directives are allowed. The latest occurrence of this directive in the source controls the discipline type of nets which are implicitly declared. Syntax 111 shows the syntax for this directive.
11.2 `default_transition
This directive specifies the default value for rise and fall time for transition filter (see 4.4.8). There are no scope restrictions for this directive. The syntax for this directive is shown in Syntax 112.
transition_time is an real value.
For all transition filters which follow this directive and do not have rise time and fall time arguments specified, transition_time is used as the default rise and fall time values. If another `default_transition directive is encountered in the subsequent source description, the transition filters following the newly encountered directive derive their default rise and fall times from the transition time value of the newly encountered directive. In other words, the default rise and fall times for a transition filter are derived from the transition_time value of the directive which immediately precedes the transition filter.
If a `default_transition directive is not used in the description, transition_time is controlled by the simulator.
11.3 `define and `undef
A text macro substitution facility allows meaningful names to be used to represent commonly used pieces of text. For example, in the situation where a constant number is repetitively used throughout a description, a text macro would be useful, as only one place in the source description needs to be altered if the value of the constant changed.
11.3.1 `define
`define creates a macro for text substitution. This directive can be used both inside and outside module definitions. After a text macro is defined, it can be used in the source description by using the ` character, followed by the macro name. The compiler substitutes the text of the macro for the string `text_macro_name. All compiler directives are considered pre-defined macro names; it is illegal to re-define a compiler directive as a macro name.
A text macro can be defined with arguments. This allows the macro to be customized for each use individually.
The syntax for text macro definitions is shown in Syntax 113.
The macro text can be any arbitrary text specified on the same line as the text macro name. If more than one line is necessary to specify the text, the newline shall be preceded by a backslash (\). The first newline not preceded by a backslash shall end the macro text. The newline preceded by a backslash is replaced in the expanded macro with a newline (but without the preceding backslash character).
When formal arguments are used to define a text macro, the scope of the formal arguments extend up to the end of the macro text. A formal argument can be used in the macro text in the same manner as an identifier.
If a one-line comment (i.e., a comment specified with the characters //) is included in the text, the comment does not become part of the text substituted. The macro text can be blank, in which case the text macro is defined to be empty and no text is substituted when the macro is used.
The syntax for using a text macro shown in Syntax 114.
For a macro without an argument, the text is substituted "as is" for every occurrence of `text_macro. However, a text macro with one or more arguments shall be expanded by substituting each formal argument with the expression used as the actual argument in the macro usage.
Once a text macro name has been defined, it can be used anywhere in a source description; i.e., there are no scope restrictions. Text macros can be defined and used interactively.
The text specified for macro text can not be split across the following lexical tokens:
· comments
· numbers
· strings
· identifiers
· keywords
· operators
Examples:
`define M_PI 3.14159265358979323846
`define size 8
electrical [1:` size] vout;
//define an adc with variable delay
`define var_adc(dly) adc #(dly)
// Given the above macro the following uses
`var_adc(2) g121 (q21, n10, n11);
`var_adc(5) g122 (q22, n10, n11);
// shall result in:
adc #(2) g121 (q21, n10, n11);
adc #(5) g122 (q22, n10, n11);
The following is illegal syntax because it is split across a string.
`define first_half "start of string
$display(`first_half end of string");
Note 1: Text macro names can not be the same as compiler directive keywords.
Note 2: Text macro names can re-use names being used as ordinary identifiers. For example, signal_name and `signal_name are different.
Note 3: Redefinition of text macros is allowed; the latest definition of a particular text macro read by the compiler prevails when the macro name is encountered in the source text.
11.3.2 `undef
`undef undefines a previously defined text macro. An attempt to undefine a text macro which was not previously defined by a `define compiler directive can result in a warning. The syntax for `undef is shown in Syntax 115.
An undefined text macro has no value.
11.4 `ifdef, `else, `endif
These conditional compilation compiler directives are used to optionally include lines of a Verilog-AMS HDL source description during compilation. `ifdef checks for the definition of a variable name. If the variable name is defined, the lines following the `ifdef directive are included. If the variable name is not defined and an `else directive exists, then this source is compiled.
These directives can appear anywhere in the source description.
`ifdef, `else, and `endif can be useful when:
- selecting different representations of a module such as behavioral, structural, or mixed level;
- choosing different timing or structural information; or
- selecting different stimulus for a given simulation run.
Syntax 116 shows the syntax for `ifdef, `else, and `endif.
text_macro_name is a Verilog-AMS HDL identifier. The first_group_of_lines and the second_group_of_lines are parts of a Verilog-AMS HDL source description. The `else compiler directive and the second_group_of_lines are optional.
`ifdef, `else, and `endif work in the following manner:
· When an `ifdef is encountered, text_macro_name is tested to see if it is defined as a text_macro_name by `define within the Verilog-AMS HDL source description.
· If text_macro_name is defined, the first_group_of_lines is compiled as part of the description. If there is an `else compiler directive, the second_group_of_lines is ignored.
· If text_macro_name has not been defined, the first_group_of_lines is ignored. If there is an `else compiler directive the second_group_of_lines is compiled.
Note 1: Any group of lines the compiler ignores still needs to follow the Verilog-AMS HDL lexical conventions for white space, comments, numbers, strings, identifiers, keywords, and operators.
Note 2: These compiler directives can be nested.
11.5 `include
This directive is used to insert the entire contents of a source file in another file during compilation. The result is as though the contents of the included source file appear in place of the `include compiler directive. `include can be used to include global or commonly used definitions and tasks without encapsulating repeated code within module boundaries.
This directive can be useful in the following situations:
· providing an integral part of configuration management;
· improving the organization of Verilog-AMS HDL source descriptions; or
· facilitating the maintenance of Verilog-AMS HDL source descriptions.
The syntax for `include is shown in Syntax 117.
The compiler directive `include can be specified anywhere within the Verilog-AMS HDL description. The filename is the name of the file to be included in the source file. The filename can be a full or relative path name.
Only white space or a comment can appear on the same line as the `include compiler directive.
A file included in the source using `include can contain other `include compiler directives. The number of nesting levels for included files are finite.
Examples:
`include "parts/count.v"
`include "fileA"
`include "fileB" // including fileB
Note: Implementations can limit the maximum number of levels to which include files can be nested, but this limit shall be a minimum of 15 levels.
11.6 `resetall
When the `resetall compiler directive is encountered during compilation, all compiler directives are set to their default values. This is useful for ensuring only those directives which are desired in compiling a particular source file are active.
To do so, place `resetall at the beginning of each source text file, followed immediately by the directives desired in the file.
11.7 Predefined macros
Verilog-AMS HDL supports a predefined macro to allow modules to be written whichl work with both IEEE 1364-1995 Verilog HDL and Verilog-AMS HDL.The predefined macro is called __VAMS_ENABLE__.
This macro shall always be defined during the parsing of Verilog-AMS source text. Its purpose is to support the creation of modules which are both legal Verilog and Verilog-AMS. The Verilog-AMS features of such modules are made visible only when the __VAMS_ENABLE__ macro has previously been defined.
Example:
module not_gate(in, out);
input in;
output out;
reg out;
`ifdef __VAMS_ENABLE__
parameter integer del = 1 from [1:100];
`else
parameter del = 1;
`endif
always @ in
out = #del !in;
endmodule
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