r31 - 22 Aug 2008 - 15:54:01 - ErikSeligmanYou are here: TWiki >  P1800 Web > SystemVerilogSpecialCommittee

p1800 System Verilog Special Committee (SV-SC) Home Page

What is the "Special Committee"?

This is a new committee formed specifically to define the new "checker" constructs. This is a proposal originally approved by the SystemVerilogAssertionCommittee, that turned out to be more controversial than originally expected. Thus this new committee was formed to come up with a full definition that all stakeholders can accept. While focused on checkers, the discussion may encompass related issues such as 'let' statements, free variables, and general assertions in procedural code.

Logistics

Current Status (updated 2008-08-22)

  • Summary: All votes complete, final versions of proposals in Mantis and approved by Champions.

Working Documents

Other Useful Links

About This Page

This is a "Wiki", which means a user-editable web page. If you are an active member of the SV-SC committee, feel free to make updates, corrections, and additions! For questions about this page, contact Erik Seligman.

-- ErikSeligman - 11 Apr 2008

Edit | WYSIWYG | Attach | Printable | Raw View | Backlinks: Web, All Webs | History: r31 < r30 < r29 < r28 < r27 | More topic actions
 
Powered by TWiki
This site is powered by the TWiki collaboration platformCopyright © by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki? Send feedback