System Verilog Assertion Committee (SV-AC)

Charter

The SV-AC is the technical subcommittee of the IEEE P1800 Working Group that is tasked with maintaining and extending the assertion support within the System Verilog language.

Website

Currently the committee website is hosted on an external wiki: http://sv-ac.pbwiki.com/. At some point, we will be moving all the data here.

-- ErikSeligman - 25 Jan 2008