Unassigned [^] (1 - 10 / 1019) 0004178 NaturalDocs references deprecated set_global_timeout instead of uvm_root:::set_timeout [VIP] RefGuide - 2012-05-25 12:57 0003052   Master issue for SV-EC Process issues [SystemVerilog P1800] SV-EC - 2012-05-24 05:27 0004177   process state question [SystemVerilog P1800] SV-EC - 2012-05-24 05:26 0004176   erroneous comment in example of fork-end block? [SystemVerilog P1800] SV-EC - 2012-05-24 04:43 0004175   Initialization of var in uvm_status_container::m_do_cycle_check method with element of queue should be protected notexisting ref [VIP] BCL - 2012-05-23 06:01 0004174   uvm_error and uvm_report_error are inconsistent [VIP] BCL - 2012-05-23 00:32 0004173   16.12, 17.3 clarify that range is bounded by constant expression [SystemVerilog P1800] SV-AC - 2012-05-22 21:54 0004162   Enable a UPF supply net to connect to an HDL signal of a real type [Power Aware P1801] 6.16 create_hdl2upf_vct - 2012-05-22 07:50 0004172 uvm_config_db::set badly broken [VIP] Resources - 2012-05-22 06:36 0004171   No VPI model defined yet for nettypes and the nets that belong to those types [SystemVerilog P1800] SV-CC - 2012-05-22 02:13	Resolved [^] (1 - 10 / 14) 0004049 Incompatible syntax of -source/-sink compared to set_isolation [Power Aware P1801] 6.42 set_level_shifter - 2012-04-06 11:37 0004028 -applies_to and -source/-sink illegal? [Power Aware P1801] 6.40 set_isolation - 2012-04-04 10:27 0004000 Clarify if legality of predefined states (DEFAULT_NORMAL, DEFAULT_CORRUPT) of a supply set can be changed or not [Power Aware P1801] 5.04.2 Power states of supply sets - 2012-04-04 10:27 0003944 Possible typo and contradictory statements w.r.t. undefined states of supply set [Power Aware P1801] 5.04.2 Power states of supply sets - 2012-04-04 10:27 0003916 Clarify how -models affect the effective_element_list semantics when specified along with -elements/exclude_elements [Power Aware P1801] 6.03 effective_element_list semantics - 2012-04-04 10:27 0003818   Add -elements and -exclude_elements to set_simstate_behavior [Power Aware P1801] 6.51 set_simstate_behavior - 2012-04-04 10:27 0003771   AKA 3771a: Define an object-oriented (syntactically bounded) approach for modeling IP block power aspects [Power Aware P1801] Additional Capabilties - 2012-04-04 10:27 0003546 AKA 3546a: Change filter options on set_iso/ls to apply to explicit ports in -elements (filtering may trigger warning) [Power Aware P1801] 6.42 set_level_shifter - 2012-04-04 10:27 0002852 Clarify whether NOT_NORMAL is one of the enumerated simstates that can be returned by functions (fixed - NOT) [Power Aware P1801] 5.04.3 Power states of power domains - 2012-04-04 10:27 0004083 Contradictory statement for VCT [Power Aware P1801] 6.16 create_hdl2upf_vct - 2012-04-04 10:20
Recently Modified [^] (1 - 10 / 4123) 0003968   2012 Ballot comment 38: sequence_formal_type includes redundant 'event' [SystemVerilog P1800] SV-AC - 2012-05-27 12:09 0004045   2012 Ballot comment 43: checker_declaration BNF does not allow nested checker declaration [SystemVerilog P1800] SV-AC - 2012-05-27 11:21 0004145   2012 Ballot comment 13. What does "variation" mean in 23.11 [SystemVerilog P1800] SV-BC - 2012-05-27 10:42 0004178 NaturalDocs references deprecated set_global_timeout instead of uvm_root:::set_timeout [VIP] RefGuide - 2012-05-25 12:57 0003937   Additional functionality for retention logic [Power Aware P1801] 6.47 set_retention - 2012-05-25 07:10 0004146   2012 Ballot comment 10: confusing definitions on p2 [SystemVerilog P1800] SV-BC - 2012-05-24 17:40 0004126   2012 Ballot comments 34, 35: allow for-loop initialization, step, termination statements to be null [SystemVerilog P1800] SV-BC - 2012-05-24 16:53 0003894   Unexpected functionality of ready-to-end [VIP] Phasing - 2012-05-24 13:53 0003052   Master issue for SV-EC Process issues [SystemVerilog P1800] SV-EC - 2012-05-24 05:27 0004177   process state question [SystemVerilog P1800] SV-EC - 2012-05-24 05:26
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