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| ID | Category | Severity | Date Submitted | Last Update | |||
| 0000215 | [SystemVerilog P1800] SV-BC | feature | 2004-09-01 16:20 | 2005-01-05 11:03 | |||
| Reporter | sv-cadence | View Status | public | ||||
| Assigned To | |||||||
| Priority | immediate | Resolution | no change required | ||||
| Status | closed | Product Version | |||||
| Summary | 0000215: Scheduling of variable initialization | ||||||
| Description |
This erratum is submitted on behalf of Steven Sharp for the issues in the thread starting at http://www.eda.org/sv-bc/hm/1950.html [^] This is well known, but has not been addressed in P1800. The semantics of variable initializers in SystemVerilog do not match the semantics defined in Verilog-2001. This is even explicitly acknowledged in the LRM. Steven Sharp sharp@cadence.com |
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| Additional Information |
http://www.eda.org/sv-bc/hm/1958.html [^] http://www.eda.org/sv-bc/hm/1959.html [^] http://www.eda.org/sv-bc/hm/1960.html [^] http://www.eda.org/sv-bc/hm/1962.html [^] http://www.eda.org/sv-bc/hm/1964.html [^] http://www.eda.org/sv-bc/hm/1974.html [^] http://www.eda.org/sv-bc/hm/1976.html [^] http://www.eda.org/sv-bc/hm/1980.html [^] From the 12/6/04 meeting: Brad moves to resolve this as not a bug. Dave seconds. For: Brad, Karen, Dave, Mark, Surrendra, *Matt (tiebreaker) Opposed: Steven, Kathy, Francoise Abstain: Danny, Don Motion Passes. Karen will notify champions & P1800 about the status of this item |
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| Tags | No tags attached. | ||||||
| Type | Errata | ||||||
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Notes |
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Karen Pieper (administrator) 2005-01-05 11:03 |
Passed in the 1/5/05 P1800 meeting. -- KLP |
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