Archive List for the RASSP Digest

Note that many of the external links are no longer valid. These newsletters are provided for archival proposes.

RASSP Educational Activities Vol. 4, June 1997 HTML Version PDF Version	Table of Contents: Editor's Corner Engineering Education: Doing Business as a Business in the 90's VHDL International's University Program A Technical Rationale for RASSP Educational Activities RASSP Educational Activities Executive Education: Key to Implementing RASSP RASSP Informational Activities VHDL CD ROM Information and Upcoming Workshops/Conferences
Technology Base Efforts Vol. 3,September 1996 HTML Version PDF Version	Table of Contents: Editor's Corner Technology Base Efforts RASSP ESDA Tools Part 1: Detailed HW/SW Codesign An Application Configuration Language for Multicomputer Tool Development Autocoding Update RASSP ESDA Tools 2: Front-End HW/SW Codesign Design Tools EaSE Trades Technical Review System-Level Design Methodology for Embedded Signal Processors Numeric and Symbolic Algorithms for Signal Processing COMET Project: Hardware/Software Cosynthesis for DSP Systems ADEPT: A Unified Environment for System Design Performance Modeling Workbench - A VHDL-Based Hardware/Software Codesign Tool ANSI C to Behavioral VHDL Translator, Ada to Behavioral VHDL Translator MAT2DSP - A MATLAB Tool for the Automatic Evaluation of the Implementation Requirements of Signal Processing Algorithms Timing Insensitive Binary-to-Binary Translation (TIBBIT) Design Tools and Architectures for Dedicated DSP Processors RASSP Model Libraries: VHDL VHDL Hybrid Models Automated Generation of VHDL Processor Models for Simulation and Synthesis Mississippi State Develops On-Line FPGA VHDL Model Generator
The Road to Enterprise Integration Vol. 3, 1st. Qtr. 1996 HTML Version PDF Version	Table of Contents: Editor's Corner The Road to Enterprise Integration Prime Development Integrated Process Control and Data Management in RASSP Enterprise Systems Enterprise Integration Technology Base The National Industrial Information Infrastructure Protocols Project (NIIIP) Concurrent Engineering Wheels Agility through Information Sharing: Results Achieved in a Production Environment
Model Year Architecture Vol. 2, 4rd. Qtr. 1995 HTML Version PDF Version	Table of Contents: Editor's Corner RASSP Model Year Architectures Prime Development The Standard Virtual Interface - An Interoperability Approach Technology Base A RASSP Approach to HW/SW Codesign A Hierarchical and Integrated Built-In Self-Test Methodology An Overview of Automated Processor Specification and Task Allocation Techniques for Embedded Computer Systems
RASSP at 24 Months Vol. 2, 3rd. Qtr. 1995 HTML Version PDF Version	RASSP at 24 Months The Second annual RASSP Conference, a Mid-Program review Second Annual RASSP Conference, Synopsis of Session 2, "Introduction to RASSP and 2nd Year Overview" Sanders RASSP Program Overview Lockheed Martin Advanced Technologies Laboratories RASSP Second Year Overview RASSP Steering Committe -- Calendar of Events
4X - Charting the Course Vol. 2, 2nd. Qtr. 1995 HTML Version	Prime Development Advance Technology Laboratories' Path to 4x Improvements Road to 4x Benchmark Program RASSP Benchmark Program: Measuring 4x Rapid Prototyping of Application-Specific Signal Processors: Current Practice, Challenges, and Roadmap Technology Base Timing Insensitive Binary-to-Binary Translation (TIBBIT) Graph Translation Tool (GrTT) RASSP VHDL Working Group Update RASSP Working Group Discusses Terms and Taxonomies
Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) Vol. 2, 1st Qtr. 1995 HTML Version PDF Version	Executive Outlook RASSP and the Lockheed-Martin Merger ARPA Manufacturing Technology Programs Ensure Military Access to Affordable Advanced Technology Prime Development VHDL Modeling for Signal Processor Development Architectures for Rapid Prototyping of Embedded Signal Processors Honeywell Develops VHDL Performance Model Library Object-Oriented VHDL Provides New Modeling and Reuse Techniques for RASSP Technology Base The Ptolemy Kernel-Supporting Heterogeneous Design VHDL Component Modeling: Impact on the RASSP Program Benchmark Program Assessing and Improving Current Practice In The Design Of ApplicationSpecific Signal Processors Editor's Corner Editorial Viewpoint Summer '95 RASSP Short Courses 95 RASSP Short Courses Calendar of Events Calendar of Events
Vol. 1, 4th Qtr. 1994 HTML Version	RASSP After One Year RASSP Education and Facilitation Conceptual Prototype Demonstrates RASSP's Future Martin Marietta RASSP Design Center Enables Design Environment Implementation The Martin Marietta RASSP Team Demonstrates and Presents Rapid Prototyping Concepts at the First Annual Conference Introduction to the Lockheed Sanders RASSP Team The Lockheed Sanders RASSP Approach The Lockheed Sanders Demonstration Program Lockheed Sanders Beta Site Program RASSP Conference Success VHDL Models The Benchmark 1 Executable Requirement Vive La Difference Acknowledgements Available Technical Publications RASSP Digest Rapid Prototyping of Application-Specific Signal Processors RASSP Steering Committee Calendar of Events