Mike Hutton

(please see bio)

Altera

Market Drivers and Technology Enablers for Embedded Processing on FPGAs

(Please see Presentation)

Mike will speak on the Market Drivers and Technology Enablers for embedded processing on FPGAs. In regard to Embedded Computing and FPGAs he will discuss the emergence of SoC FPGAs and the related Hardware-Software Programmability issues. (more)

Hans Spanjaart

(please see bio)

Altera

Moderator

Sri Ganta

Senior Principal IC Design Engineer (please see bio)

Broadcom

Why Early DFT is Compelling

(Please see Presentation)

Today's ASICs adopt complex design techniques like Dynamic Voltage Frequency Scaling (DVFS), Switchable Power Domains, Variable Voltage Domains etc. to meet the market needs. Traditional DFT approaches, where DFT insertion and verification starts only at netlist level, will no longer fulfill testing needs, and would have detrimental impacts on schedules. (more)

Frank Schirrmeister

Senior Director (please see bio)

Cadence

System-Level EDA 2015 – Who’s Problem is Software Anyway?

(Please see Presentation)

This presentation will chart a potential future how the markets for EDA and Embedded Software will have to converge based on user requirements. Starting from an analysis of the changing development responsibilities in the design chain from consumers, system, independent software, semiconductor and IP companies, this presentation will define requirements for hardware/software development across application domains. (more)

Tom Spyrou

AMD Fellow (please see bio)

AMD

Parallel EDA: A User's Perspective

(Please see Presentation)

EDA companies are focused on providing parallel solutions to improve the runtime of their applications. These solutions need to scale reasonably well to be worth deploying and be deployable in the user’s context. Most design teams have access to some kind of load / machine resource sharing system that gives them access to their cpu’s. EDA applications need to work cooperatively with such systems.

Sangeeta Aggrwal

Software Engineer (please see bio)

Synopsys

Tackling Runtime Variance on NUMA architecture

(Please see Presentation)

James Colgan

Co-Founder and CEO (please see bio)

Xuropa

The CAD-Less Semiconductor Company. Where is the Cloud for Electronics Design and who will use it?

(Please see Presentation)

In the nineties foundries commoditized semiconductor manufacturing and the fab-less semiconductor company was born. Companies like Broadcom and Qualcomm leveraged the power and scalability foundries enabled and invested in intellectual capital rather than manufacturing capital. Coming from nowhere, fab-less companies created and continue to dominate their respective market segments. (more)

Xiren Wang

(please see bio)

Nimbic

Electromagnetics Simulation using HPC in a Cloud

Kiron Pai

Technical Lead

Intel

Improving User Productivity in a Cloud Environment

(Please see Presentation)

This is about about the challenges of managing a Geo Dispersed SoC Design Environment at Intel. This talk will lay out the problem statement and offer some solutions hints, inviting EDA vendors and academic community to develop future solutions. (more)

Azadeh Davoodi

Assistant Professor, Department of Electrical and Computer Engineering (please see bio)

U. of Wisc

Highly Distributed and Confidentiality Preserving Global Routing

(Please see Presentation)

Naresh Sehgal

SW Architecture Manager (please see bio)

Intel

Optimizing a Cloud with SLAs and QoS

(Please see Presentation)

Gary Smith

Founder and Chief Analyst (please see bio)

GarySmithEDA

Reviewing the New ITRS Power Model

(Please see Presentation)

At last year’s ITRS, we began the process of building a new power model for the average high-end mobile SoC. It proved to be a far more difficult task than we had imagined. The final model was completed in mid-January of this year. (more)

Ian Ferguson

Director of Server Systems and Ecosystem (please see bio)

ARM

Energy Efficient Servers for the Data Ctr

(Please see Presentation)

The transition to a cloud computing world is disruptive for the server market. End users like Facebook and Google are defining their own systems, and owning their value chains - at both the hardware and software level. ARM believes that this market will become increasingly segmented from the point of view of the types of workloads and software running on these systems. (more)

Qi Wang

Group Director of Solutions Marketing (please see bio)

Cadence

Low Power Design: Is the Problem Solved?

(Please see Presentation)

During the past few years, the EDA industry has made some significant advancement in developing tool flows and methodologies to automate advanced low power design techniques. However, most of the work done focused on how to automate advanced low power design techniques such as power gating or dynamic or adaptive voltage frequency scaling, so that such advanced techniques can be deployed in mainstream designs. Areas that have not had equal investment include power estimation and optimization. (more)

Grant Martin

Chief Scientist (please see bio)

Tensilica

Power-Aware Software - Is that all there is?

(Please see Presentation)

We are too often bound by conventional thinking in architecting and designing systems and in writing software to run on them. One aspect of conventional thinking about systems is to assume that designs are implemented by a combination of dedicated hardware, and software running on someone else's fixed instruction set architecture processor. (more)

Jim Hogan

Private Investor (please see bio)

Vista Ventures

SoC Realization: The Next Horizon

(Please see Presentation)

Relentless push for higher quality user experience with minimum system cost and power are key. Feature convergence in Video, Voice, Data, etc. in consumer devices, led by the smartphone, is impacting SoC realization. Popularity of tablets adding to the equation. What affect does this have on system companies relative to Fabless and IDMs? How will this impact the realization of SoC's?

Riko Radojcic

Director of Engineering (please see bio)

Qualcomm

Roadmap for Design and EDA Infrastructure for 3D Products

(Please see Presentation)

An outline of the various flavors of 3D technology is provided and the corresponding design and EDA challenges are presented, and our design implementation strategy is summarized. (more)

Arif Rahman

Product Architect (please see bio)

Altera

FPGA Design Challenges

(Please see Presentation)

Steven Pateras

Product Marketing Director, Silicon Test (please see bio)

Mentor

Evolving BIST Solutions for 3D-ICs

(Please see Presentation)

BIST solutions have seen a steady increase in adoption over the past few years as design complexities and demands for high-quality test have continued to rise. The upcoming growth in 3D integration will drive increased usage of existing BIST solutions as well as drive the need for new BIST capabilities. (more)

Marc Greenberg

(please see bio)

Cadence

3D-IC is now real - Wide-IO is driving 3D-IC TSV

(Please see Presentation)

Bassilios Petrakis

(please see bio)

Cadence

What does it take to build an End-to-End Test Flow for 3D-IC stacks?

Sandeep Goel (TSMC) is Co-Author of this presentation

(Please see Presentation)

Steve Leibson

Technology and Marketing Consultant

Cadence

Moderator

Herb Reiter

Principal (please see bio)

EDA 2 ASIC

3D-IC Panelist

(Please see Presentation)

Being the first panelist, Herb will expand on the panel's title and briefly address short-, medium- and longer-term EDA requirements for making 2.5/3D technology cost-effective and successful.

Samta Bansal

Senior Manager, Product Marketing, SoC Realization (please see bio)

Cadence

3D-IC Panelist

(Please see Presentation)

Tablets and smartphones are demanding more and more memory bandwidth for HD Video, 3D Gaming, computing and image processing, without substantially increasing power. 3D-IC and Through-Silicon-Via (TSV) are technologies that provide a substantial increase in bandwidth between dies that can also reduce energy per bit transferred, and offers improvements ranging from 10X to 50X in key metrics like number of connections, connection capacitance, and connection length compared to some current methods of die-to-die connection. (more)

Dusan Petranovic

TME (please see bio)

Mentor

3D-IC Panelist

(Please see Presentation)

A verification methodology for 3D-ICs is presented, including connectivity checking and parasitic extraction. An example is given to illustrate a true 3D-IC stack verification using a GDS based flow. (more)

Deepak Sekar

Chief Scientist (please see bio)

Rambus

3D-IC Panelist

(Please see Presentation)

Steve Smith

Senior Director, 3D-IC Strategy and Marketing (please see bio)

Synopsys

3D-IC Panelist

(Please see Presentation)

Phil Marcoux

(please see bio)

PPM Associates

3D-IC Panelist

(Please see Presentation)