Sponsored by
In cooperation with
ACM/SIGDA
|
Technical Program
SUNDAY, APRIL 21 |
| 6:00 - 8:00 pm |
Registration and Reception |
| |
MONDAY, APRIL 22 |
| 8:00 - 8:30 am | CONTINENTAL BREAKFAST |
| 8:30 - 8:35 am |
WELCOME
Andrew B. Kahng (UCSD), General Chair
Gary Smith (Gartner/Dataquest), Program Chair
|
| 8:35 - 9:30 am |
KEYNOTE 1
"Decreasing Product Development Cycles in a Rapidly Growing Company",
Dan Smith (Nvidia)
[slides]
|
| 9:30 - 9:45 am | Break |
| 9:45 - 12:00 pm |
SESSION 1: HIGH-LEVEL MODELING I
Moderator: Richard Goering (EE Times)
0945-1005 "The Future of High-Level Modelling and System Level
Design: Some Possible Methodology Scenarios",
Grant Martin (Cadence Design Systems)
[paper,
slides]
1005-1025 "Bridging the High-level and Implementation Divide:
Mission Impossible?",
Victor Konrad (Intel)
[paper,
slides]
1025-1045 "SystemC abstractions and design refinement for HW-SW
SoC designs",
Dundar Dumlugol (CoWare/SystemC)
[slides]
1045-1105 "SpecC Methodology for High Level Modeling",
Rainer Doemer (UCI/SpecC)
[paper,
slides]
1105-1125 "High-level Design Using General-Purpose Languages",
John Sanguinetti (FORTE/Cynlib)
[paper,
slides]
1125-1200 Moderated Discussion, Workshop Attendees
Panel : High Level Modeling Methodology: Will it ever be mainstream?
|
| 12:00 - 1:15 pm | Lunch |
| 1:15 - 3:15 pm |
SESSION 2: HIGH-LEVEL MODELING II
Moderator: Sandeep K. Shukla (UCI)
1315-1345 "A Methodology for SoC Top-Level Validation using
Esterel Studio",
Lionel Blanc, Amar Bouali, Jérôme Dormoy and
Olivier Meunier, (Esterel Technologies)
[paper,
slides]
1345-1415 "Breaking Down Complexity for Reliable System-Level
Timing Validation",
Dirk Ziegenbein, Marek Jersak, Kai Richter, and Rolf Ernst,
(Technical University of Braunschweig)
[paper,
slides]
1415-1445 "TACO: Rapid Design Space Exploration for Protocol
Processors",
Seppo Virtanen, Johan Lilius, Tero Nurmi and Tomi Westerlund,
(Turku Centre for Computer Science)
[paper,
slides]
1445-1515 Moderated Discussion, Workshop Attendees
|
| 3:15 - 3:30 pm | Break |
| 3:30 - 5:30 pm |
SESSION 3: HW/SW CO-DESIGN
Moderator: Rajesh Gupta (UCI)
1530-1600 "Platform-based Design: Report from the Front",
Daniel Martin, Sagheer Ahmad, and Kambiz Khalilian
(Infineon Technology)
[paper,
slides]
1600-1630 "Platform-Based Design and the First Generation Dilemma",
Jiang Xu and Wayne Wolf (Princeton University)
[paper,
slides]
1630-1700 "Platform-based Co-Design and Co-Development:
Experience, Methodology and Trends",
Grant Martin and Jean-Yves Brunel
(Cadence Design Systems)
[paper,
slides]
1700-1730 Moderated Discussion, Workshop Attendees
|
| 6:00 - 8:30 pm |
DINNER
Invited Talk:
"Evolving ASIC Methodology to Adapt to Technology and EDA Tool
Advances", Tom Russell
[slides] (IBM)
|
| |
TUESDAY, APRIL 23 |
| 7:30 - 8:00 am | CONTINENTAL BREAKFAST |
| 8:00 - 9:15 am |
SESSION 4: RTL METHODOLOGY
Moderator: Linda Feldt (Intel)
0800-0830 "Managing Risk in Block Based Designs: A Front End
Acceptance Methodology",
Kumar Venkatramani and Stefanus Mantik
(Cadence Design Systems)
[paper,
slides]
0830-0900 "Policy-Based RTL Design",
Bhanu Kapoor and Bernard Murphy
(Atrenta)
[paper,
slides]
0900-0915 Moderated Discussion, Workshop Attendees
|
| 9:15 - 9:30 am | Break |
| 9:30 - 12:00 pm |
SESSION 5: THE FUTURE OF RTL SIGNOFF
Moderator: Gary Smith (Gartner/Dataquest)
0930-0950 "Design Tool Advances Drive ASIC Signoff Paradigm Shift",
Tom Russell (IBM)
0950-1010 "Providing Physical Vision to RTL Designers",
Shankar Krishnamoorthy (Synopsys)
[slides]
1030-1050 "Noise in the RTL Signoff Flow",
Vivek Joshi
[slides] (Intel)
1050-1110 "Evolution of Sign-off Models",
Tommy Eng (Tera Systems)
1110-1130 "Engagement Model Dependent Sign-off",
Dan Deisz (LSI Logic)
[slides]
1130-1200 Moderated Discussion, Workshop Attendees
|
| 12:00 - 1:30 pm |
LUNCH AND KEYNOTE 2
"Collaboration Methodologies and Best Practices for IP Development
and SOC Design", Dennis Harmon (Synchronicity)
[paper]
|
| 1:30 - 3:30 pm |
SESSION 6: ANALOG MIXED SIGNAL
Moderator: Juan-Antonio Carballo (IBM)
1330-1400 "A New Methodology for Analog/Mixed-Signal (AMS) SoC Design
that Enables AMS Design Reuse and Achieves Full-Custom Performance",
Kazuhiro ODA (Toshiba),
Lou Prado, and Anthony J. Gadient (NeoLinear)
[paper,
slides]
1400-1430 "Synthesizable full custom mixed signal IP",
Mar Hershenson and Dave Colleran
(Barcelona Design)
[paper]
1430-1500 "A Revolutionary New Solution to Unified RF Systems
and Circuit Design",
James Spoto (Applied Wave Research)
[paper,
slides]
1500-1530 Moderated Discussion, Workshop Attendees
|
| 3:30 - 3:45 pm | Break |
| 3:45 - 5:45 pm |
SESSION 7: COST-EFFECTIVE DESIGN
Moderator: Michael Riepe (Magma Design Automation)
1545-1615 "Cost Savings through Reuse",
Aparna Dey (Synchronicity)
[paper,
slides]
1615-1645 "IP Authoring and Integration for HW/SW Co-Design and
Reuse - Lessons Learned",
Frank Schirrmeister, Martin Meindl and Stan Krolikoski
(Cadence Design Systems)
[paper,
slides]
1645-1715 "Reuse and Quality Enhancement via Computation and
Distribution of Component Derivative Rewards",
Juan-Antonio Carballo, Wendy Belluomini, Robert Montoye
and David Cohn (IBM Research)
[paper,
slides]
1715-1745 Moderated Discussion, Workshop Attendees
|
| 5:45 pm | Adjourn |
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