In an ideal world, synthesis tools would be able to understand all of the FPGA architectures available and would be able to take advantage of the special features that these devices provide without the interference of the designers. In the real world, however, this is not the case, for applications that are speed and area intensive, designers have to be aware of the consequences of the coding style that they choose to follow. In addition, an understanding of the FPGA's architecture, the synthesis tool and the back end software is also a requirement. In this paper a description of certain VHDL constructs as well as their synthesis results is going to be discussed illustrating some of the shortcomings in the High Level Design Flow for LUT based FPGAs.
The IEEE VITAL standard provides modeling guidelines and a set of predefined packages which facilitate the acceleration of designs during simulation using models from VITAL compliant library. In this paper, we highlight the various VITAL features used in a typical ASIC library, the associated modeling trade-offs, a development approach based on existing source libraries and related issues. The paper also describes few limitations of VITAL in addressing sign-off requirements and alternative implementations developed for addressing such requirements.
The recently approved VITAL standard will permit many of the drawbacks presented by the use of VHDL at gate level to be overcome. It does not, however, address one of the basic design process stages at gate level: fault simulation. With the aim of integrating this stage in the VHDL design process, several proposals have appeared in recent years for voltage fault modeling for VITAL descriptions [1]. These do not take into consideration a fault type which has appeared recently and which is of growing importance: current faults. The main purpose of the present work is to propose a current fault model for VHDL gate-level descriptions which are VITAL compliant. To do this, it was necessary to define modeling techniques for the current flowing through a logic gate.
Memories are an important component in ASIC designs. As million gate ASICs are becoming reality, there is an increasing need to model memory devices with a high level of accuracy and simulation efficiency. There are no modeling standards available currently to model memories in VHDL. This paper describes the functional/timing aspects of VHDL memory models, their implementation, and issues involved in various approaches for modeling memories in VHDL. This paper also presents a generic memory interface package used in the development of VHDL models of ASIC memories.
This paper explores issues relating to cooperative software and hardware development, focusing on different stages in a design cycle supported by VHDL-based design and development techniques. Since most commercial tools focus on implementation, integration, and debug, rather than early life-cycle stages such as requirements capture and design, the application of these tools requires different techniques, goals, and expectations. The experiments and trade-offs appropriate for the different stages in the design cycle are evaluated, as well as the performance of the tools and models.
To address the separation between the hardware and software domains, this paper presents an abstract hardware/software model employing a unified representation. The model supports early hardware/ software evaluation and trade-off exploration. In addition, systems can be evaluated at different levels of detail, allowing those aspects of interest to be focused on. The benefits of a unified representation are also discussed. Some examples are presented to illustrate the abstract hardware/software model and demonstrate the concepts and ideas embodied in the paper.
This paper addresses the applicability and use of processor synthesis tools and VHDL to support a codesign methodology. It suggests the features required for a viable tool to support high engineering productivity of digital processing systems. It reports on their application to communications and signal analysis digital hardware designs and involves pulse detection and waveform processing of high rate or complex communications and radar signals. This use is appropriate to the Consumer Electronics, Telecommunications, and Aerospace industries and the Military where requirements for minimum size, weight, and power prohibit t h e exclusive use of Commercial Off-The-Shelf (COTS) processor solutions. A particular processor synthesis tool is used as an example in this discussion.
Applications that execute on high performance multiprocessors often must meet stringent real-time constraints. The interaction of the applications, the runtime scheduler, and the multiprocessor architecture will have a significant impact on performance. This presents an outline of the efforts of the Center for Semicustom Integrated Systems and the Naval Research Lab to develop a performance modeling environment for processing graphs running on multiprocessors. VHDL is used to model the target multiprocessor architecture. A scheduler written in C or C++ is used to assign transitions, which are the computational elements in the processing graph, to subprocessors in the VHDL hardware model. This assignment process may be dynamic. The transition' s execution time can be estimated as a function of its input parameters through the application of multivariate regression techniques. The transition's estimated execution time is passed from the scheduler to the VHDL hardware model when the transition is assigned to a subprocessor. The transition's timing may vary on successive executions if the transition's input parameters change. The interaction between the scheduler and the VHDL model takes place through a VHDL-to-C interface.
This paper presents a new approach towards support of rapid system virtual prototyping, melding current hardware and software development environments, called Virtual System Integration. It provides for the rapid execution of target software applications as they are simulated in a virtual system modeled in VHDL or Verilog. This approach also supports the respective development tools and debugging environments available today to hardware and software engineers. Indications from early adopters of this new technology appear very promising. One such case is discussed.
In this paper a model is presented that allows translation of close to full VHDL (excluding time constructs) to a control-data flow graph. The syntax based translation leaves the VHDL execution mechanism in the graph. Behavior preserving transformations are used to remove the execution mechanism.
In this paper we address the problem of partitioning register level designs for implementation on multiple FPGAs. The partitioner uses a modified multi-way Fiduccia-Mattheyses algorithm. Cost estimation functions needed by the partitioner to estimate the re- sources needed by the design on a FPGA have been developed. The methodology for estimation of resources on an FPGA (function generators, flip-flops and CLBs), and partitioning of the design are discussed in detail.
This paper describes an experiment demonstrating the value of computer-based reasoning in hardware design. An interactive theorem prover is used to prove that VHSIC Hardware Description Language (VHDL) designs meet their specifications. Hardware designs and a formal logic notation are related by way of a formal semantics for VHDL developed by Rome Laboratory under a contract to Odyssey Research Associate Inc. (ORA). The advantage of starting with a formal specification is that the specification is precise and compact. In hierarchical design the higher level designs depend only on the specifications of components, not their architecture. Each refinement towards an implementation may be traced back to the original specification for compliance, i.e. verification. In verification it is not necessary to reason about delta cycle activity. This paper describes the process of performing a formal proof that a VHDL design satisfies its specification. T h e experiments make use of the ORA Larch/VHDL proof environment.
In this paper, we propose a formal method to verify equivalence of two Finite State Machines described in VHDL. This verification is done automatically with PSM (Proof State Machines) tool, by symbolic forward transversal of a partitioned transition relation, derived from the two VHDL descriptions. We present the algorithms applied to perform the verification and give experimental results of the verification of various VHDL descriptions.
In this article, use of VHDL to model and simulate optoelectronic devices and interconnection networks is presented. In order to model the optoelectronic devices such as waveguide splitter, waveguide bending, wavelength division (De)multiplexing, an optical package was designed. In this package we defined the optical signal properties and the corresponding computation modules needed to determine the optical signal propagation delay, loss and other parameters. We then build an optical link network using the optical device models we developed. Simulation results show that the use of VHDL and EDA system based on VHDL to model and simulate optoelectronic systems reduces the design and verification time, improves productivity, yields technology-independent system designs, and makes the design refinement process efficient and fast. Keywords: VHDL. Simulation, Optoelectronic Link Simulation.
This paper describes the design and validation methodology used in the development of a complex Network Computer Interface Card, and two monolithic ICs. We have used VHDL to specify and validate the system from a functional point of view (pre-synthesis simulations). After the logic synthesis step, we have used non-VHDL descriptions for both the circuits and the test-data. The stimulus and expected-responses for the non-VHDL simulator (time-vector format) have been obtained automatically during a pre-synthesis (VHDL) simulation run. To make this process independent from both the VHDL-simulator and the logic simulator, the time-vector stimulus and responses files have been generated by using procedural VHDL testbenches.
This paper describes the design a set of critical functions performed by a B-ISDN terminal equipment, with a SDH-based physical layer and an AAL of type 3/4. These functions are: synchronous and self-synchronizing scrambling / descrambling, CRC generation / check and error-correction based on Syndrome calculation. The high data-rate at the B-ISDN dissuades the use of simple LFSRs and a more complex parallel implementation must be used. The use of VHDL synthesis tools allows to design these functions in a simple and direct way.
This paper examines the application of novel formal methods techniques to assist in the automatic generation of correct RT-level VHDL code. Of particular interest is a class of designs which are "protocol-limited" in their specification, having to meet complex temporal and physical I/O constraints. It is difficult to easily model this in VHDL and a technique which makes this easily realisable is illustrated on an example which is a complex DSP application.
Design Errors are all of the non-equalities between the desired functionality and the implemented design. They lead in many cases to a new IC fabrication that means higher NRE (Non Recurring Engineering) costs and delay in the time to market. This paper deals particularly with VHDL Design Errors. They are classified and modeled, and a new general methodology for correctability of design errors (i.e. the ability to correct them even after the fabrication) is presented. Afterwards, this method is applied for a subset of error groups and discussed in detail. Some guidelines for making a good and reasonable trade-off between the correctability and its resultant overheads (such as area and speed) are presented too.
When a VHDL design is synthesized from a specification, it becomes necessary to test the synthesized design description and eventually the actual device. While test vectors and a testbench may already exist for the specification, there may be many differences in the two designs that make the original testbench and test vectors unusable for the synthesized design/actual device. The new design may have extra pins not included in the original design, and most likely the timing information will have changed from the original. This paper discusses a methodology for transforming a VHDL/WAVES testbench for the specification model into a VHDL//WAVES testset to test either a synthesized design or the actual device.
This paper describes a new automated approach to generate simulation test bench models. A distinguishing feature of this approach is the use of abstraction models to serve as inputs to the test bench generation process. The approach implementation within a new VHDL test bench synthesis tool is demonstrated on an illustrative example. This new tool is evaluated with respect to existing tools and shown to provide better support for multi-level simulation environments. Future work is discussed for implementing advantageous aspects of competing approaches.
In this paper a description of the evolution of the usage of VHDL in Spain is provided. Current research and development activities using VHDL at the main companies, Universities and research centers are described. When possible, references have been included in order to facilitate the interested reader access to more detailed information.
This paper presents an overview over current research activities in the field of HDL based design in German universities, research laboratories and companies. Major emphasis is put on system design due to the fact that this is the major domain of German electro-technical industry.
Since the introduction of the IEEE standard VHDL (Std. 1976-1987) the use of this hardware description language and research activities closely related to it is rapidly grown. At the presentation a summary is presented of the VHDL activities in the Netherlands.
This presentation is an overview of the research on and around VHDL in France, Italy and French speaking Switzerland. The teams covered by this survey are well known in Europe, for their participation in the VHDL User's Groups, and for their publications. The period covered is 1991-1995, although some groups have started their VHDL activities several years before.
For the next few years, the coexistence of VHDL and Verilog is inevitable within the user community. Existing investments in designers, designs and tools preclude any rapid changes from either language to the other. However, the continued development of separate VHDL and Verilog tools increases the costs to end users. In order to reduce the cost of supporting two languages and allow reallocation of investment toward greater functionality, this paper examines the implications of analyzing VHDL and Verilog into a common intermediate form based on a superset of VHDL semantics. We identify the semantic extensions needed to support such a hybrid intermediate format. The most significant changes are to the underlying temporal semantics and to support Verilog's globally visible naming schema. Additions to the type system, programming interface and sequential execution model are modest. The paper concludes that there is enough overlap between VHDL and Verilog semantics that developers of new tools should seriously consider developing bilingual tools (See Figure 1).
VHDL simulations running on shared memory multiprocessors have a global events list. The list is updated by multiple processors. In a traditional implementation, a processor locks the entire list structure, updates the list, and then unlocks the structure. We present data structures and algorithms that allow multiple processors to update the list concurrently. On processors with compare & exchange read-modify-write capability the problem is trivially simple and does not require a lock at all. On processors that do not have compare & exchange capability, events are inserted concurrently except when two or more processors attempt to insert an event between the same two elements of the list. A local lock is used to resolve this contention and let one processor insert the event at a time. Another processor inserting an event between any, other two elements in the list can still do so concurrently with the first processor. Using exchange read-modify-write capability, we provide contention free busy-waiting for the processors that may have to wait for the same local lock. We further ensure that the waiting processors are served in a FIFO manner. The entire linked list structure is not locked under any circumstances. This will greatly help performance first by allowing concurrent updating and second by using a contention free local lock when a lock is needed.
This paper presents an analogy between structural and object-oriented properties with the object to show a migration path for the introduction of the software methodology object-orientation in the hardware design process. First VHDL structural description capabilities and object-oriented principles are described. Afterwards structural VHDL is analyzed under the aspect of object-oriented description methods. It is shown how a configuration can support "static" polymorphism. Incremental development and implementation as included in inheritance mechanisms can be modeled with structural statements. However some overhead is required Thus, an inheritance mechanism, already known from real-time object oriented modeling and similar to ADA tagged types, is proposed for VHDL entity, architecture and component declarations. Application examples and an outlook to genericity conclude the paper.
As hardware design increases in complexity, so does the development process. To this effect, it is envisaged that the use of analysis techniques focusing on design abstraction and reusability can be advantageous in tackling the issues that conventional analysis and design techniques failed to address. Object-Oriented design methodology has recently had a considerable impact in the software design community as it is tightly coupled with the handling of complex systems. Object-Orientation concentrates on data rather than functions since, throughout the design process, data are more stable than functions. Methodologies for both hardware and software have been introduced through the application of HDLs to hardware design. Common design constructs and principles that have proved successful in software language development should therefore be considered in order to assess their suitability for HDLs based designs. In this paper we will propose the specifications by Bournemoth University and IBM, UK for an alternative Object-Oriented extension to VHDL: The Classification-Orientation. Related work will be reviewed, and the motivations for the proposed implementation will be introduced. A detailed Backus-Naur form of the proposed new grammar will be presented. An example of the design of an FIR filter will be used to illustrate the modelling capability achieved through the use of the Object-Oriented extensions to VHDL. The concept of the object model will be discussed and conclusions will be drawn with regards to simulation and synthesis issues.
The SAVANT project is a joint effort between the University of Cincinnati and MTL Systems, Inc. to build an extensible, object-oriented intermediate form (IF) for VHDL. The primary goal of SAVANT is to stimulate the integration of VHDL technology into the research CAD community. The use of an extensible object-oriented format means that the class definitions of the IF can be extended with additional data and method definitions; user's benefit from the fact that the nodes are self defining and that overloading can be exploited for building IF node processing. Since the IF is fully extensible, no procedural interface is provided or needed. The SAVANT project includes a C++ implementation of the IF. Important in this implementation is the design of a class hierarchy that allows extensibility of the IF without allowing the modification of the core IF definition. Essentially this is achieved by organizing the base IF nodes into two parts, namely: a set of "base" class definitions, and a corresponding set of "final" derived class definitions. User defined extensibility is achieved by (i) deriving new (user defined) classes from the "base" node definitions and (ii) revising the inheritance path of the "final" nodes to the new user defined classes. This SAVANT project includes a suite of software tools to implement a VHDL qparser to IF translator (oiled SCRAM) and extensions to the IF to support node rewriting and code generation. In particular, the static rewriting rules from the RASSP formal modeling project am implemented as a collection of overloaded methods called transmute. This rewriting eliminates several of the redundant nodes from a specific instance of the IF (for example replacing concurrent signal assignment statements with their equivalent process statement representation). Code generation capabilities exist to regenerate VHDL or to generate C++ suitable for linking with the TyVIS VHDL simulation kernel (the UC parallel VHDL simulation kernel). The SAVANT project is more fully documented on the www at http:/www.mtl.com/projects/savant and http:/www.ece.uc.edu/~paw/savant.
ARPA's Rapid Prototyping of Application-Specific Signal Processors (RASSP) program has promoted new hardware-less methodologies in system-level design automation, wherein starting with application-specific requirements a multiboard hardware/software system is prototyped taking into account design efficiency, time-to-market, testability, and upgradeability considerations. This paper describes an implementation of this methodology in VHDL. In addition to a discussion of the virtual prototyping techniques being developed by the RASSP program, the novel education and training capabilities and methods being developed by the RASSP Education & Facilitation (RASSP E&F) program are also presented. The objective of the RASSP E&F program is to promulgate the RASSP technology through education and other technology and information (http://rassp.scra.org) transfer activities to the wider rapid prototyping and VHDL user community within the industry, the government, and the academia.
Simulatable Specifications (SimSpecs) have been identified as a key means for rapidly developing high quality electronic product designs. The Air Force's Continuous Electronics Enhancements Using Simulatable Specifications (CEENSS) program has been initiated to explore the application of Simulatable Specification technology to the design and development of Printed Circuit Board/Line Replaceable Module mixed signal electronic products. The CEENSS program is focused upon the following objectives: The ability to design products which have a very high probability of correctness, Achieving a radical reduction in the time and cost of product design, The ability to design products with significantly reduced design obsolescence, and Achieving a radical reduction in the time and cost for product redesign/retrofit. A major contributor to the time and cost of original product design and design modification/retrofit is the excessive integration and test effort required to fix problems caused by faulty requirements. This integration and test delay is caused by detection of problems, determination of problem causes, and design modifications to correct the problems. The use of formal SimSpecs makes possible the development of complete, consistent, unambiguous requirements specifications which will significantly reduce integration and test problems which stem from requirements problems. The utilization of SimSpecs in product design verification at each level of design will catch a large percentage of design errors in the step where they are introduced rather than deferring them all until integration and test where they are more complex and expensive to correct. SimSpecs are written in VHDL, which allows them to be formal, unambiguous representations, and enables verification through execution. The use of SimSpecs as a primary design capture mechanism enforces the development of technology independent design representations which will significantly enhance users' ability to incorporate new technology into a design without reinventing the whole design. A key approach to producing high confidence designs is to reflect manufacturing and test aspects of the system in the SimSpec and to verify manufacturability and testability of the design as core elements of the product design verification process.
Industry standards, such as the VHSIC Hardware Description Language (VHDL) and the Waveform And Vector Exchange Specification (WAVES), are critical elements in being able to integrate the design and test cycles. When performing top-down designs based on these standards, the descriptions necessary for system life cycle support are obtained and captured during design. Together, VHDL and WAVES provide a powerful mechanism for concurrent engineering practices by allowing digital stimulus and response information to be freely exchanged between multiple simulation and test platforms. WAVES is defined as a syntactic subset of VHDL, and as such, can be simulated against the VHDL model during design to verify functionality and timing. Further, after the hardware is built, the same WAVES data may be ported to the test environment for electrical test. This process assures that the same source stimulus and timing that were used during design are applied during electrical testing. VHDL and WAVES design validation methods are a major advancement in assuring that digital electronic systems are truly designed for the goal of two-level maintenance and on-equipment fault diagnosis. The authors will discuss the WAVES re-ballot requirements in terms of a complete top-down design methodology. This paper will also discuss the current development of WAVES based software tools and products to support VHDL model verification.
Easily Updateable Testbenches A key to lowering life cycle support cost As a system evolves, model testing requirements frequently change Model tests are encapsulated in the testbenches