With increasing emphasis in the design environment being placed on requirement flow down and traceability through the design hierarchy, new methodologies are evolving to meet this goal. These new methodologies are based on a shift to a new design paradigm that no longer is based on gate level design, but is now based on requirements analysis, behavioral design, logic synthesis, hardware acceleration and computer aided hardware prototyping as the foundation.
This presentation will highlight Honeywell's experience in using VHDL as a specification for a graphics display system. During the Graphics Processor Definition (GPD) Program, Honeywell developed a VHDL performance model which embodied the characteristics of the system architecture. During the next phase of the program, the Cockpit Display Generator (CDG) contract, Honeywell is developing a functional model of the architecture. The VHDL model is being used, in conjunction with the Segment Definition Document (SDD), and various 2167A documents, to fully specify the system. This presentation highlights how VHDL fits in with this process, how the use of VHDL affects the traditional specification and documentation method, the problems encountered during this process and their implications, and recommendations for changes required to make a VHDL specification process a reality. The technical details of our methodology were presented during the performance modeling tutorial at this conference.
This presentation will highlight Honeywell's experience in using VHDL as a specification for a graphics display system. During the Graphics Processor Definition (GPD) Program, Honeywell developed a VHDL performance model which embodied the characteristics of the system architecture. During the next phase of the program, the Cockpit Display Generator (CDG) contract, Honeywell is developing a functional model of the architecture. The VHDL model is being used, in conjunction with the Segment Definition Document (SDD), and various 2167A documents, to fully specify the system. This presentation highlights how VHDL fits in with this process, how the use of VHDL affects the traditional specification and documentation method, the problems encountered during this process and their implications, and recommendation8 for changes required to make a VHDL specification proceee a reality. The technica details of our methodology were presented during the performance modeling tutorial at this conference.
The purpose of our research is to create two VHDL models of the i960 MX processor. These models will be used in the development of an embedded system running Ada programs on multiple i960 MX processors. The system designer will choose which model to use based on the amount of information required from the simulation. The two models produced will be a high-level model and a low-level model.
This presentation will provide an overview of synthesis technology, from combinational optimization designed for optimizing a detailed gate-level logic design for timing and area, to High-level synthesis including resource sharing, system partitioning and scheduling. The presentation will also distinguish the three domains of representation -- behavioral, structural, and physical -- and discuss the tools that are applicable to each domain at each level of abstraction.
VHDL can help contractors meet two objectives: reduction of LSI design cycle time and generation of technology independent models to satisfy DoD requirements. If synthesizable RTL VHDL is written following certain design rules, logic-optimized producible LSI can be efficiently designed. VHDL provides the advantages of reusability and documentation. RTL simulations should match LSI tool generated simulations.
The VHDL language has been used for a wide range of models. One modeling style used by ASIC designers is to create a structural network of ASIC cells. Each of the cells represents a logic cell in a target ASIC vendor library. The network is usually created either manually or using logic synthesis.
ITT Avionics has adopted an ASIC design methodology based on high level RTL VHDL synthesis in order to improve the development of today's large complex ASICs. This presentation will compare ITT's VHDL based design flow to more conventional techniques and will discuss the experiences of bringing this process on line, including training, design tools, technical and management problems, and cost and schedule benefits.
The effort for developing a standard VHDL library containing packages for synthesis has led to progress in the following areas:
A behavioral model described as a statechart is based not only on modes and transitions, but on events, conditions and different types of data items too. Although statecharts resolve the blow-up phenomena associated with state transition diagrams, a realistic system is not described as a single statechart. This paper introduces scoping of elements in a model based on several statecharts and its impact of testing.
"Situational awareness" has been identified as the single most critical factor in improving mission effectiveness in fighter aircraft. Situational awareness can be described as having knowledge of the current and near-term disposition of both friendly and enemy forces within a volume of space. This knowledge or information in future military aircraft will be presented in the cockpit using computer or electro-optically generated displays. Thus, display technologies are critical for providing a pilot the situational awareness necessary to fly, fight, and survive in the future combat environment.
There are two important early stages in the design of complex systems, modeling of the system (operational) specification and modeling of the system performance. In this paper, we propose a link between operational specification and performance modeling via VHDL. We show by an example, how the models can be made to interact, yielding a synergy leading to design efficiency and improved modeling accuracy. While this paper does not provide concrete rules to solve the general problem of linking these two models, it justifies the usefulness of such a link through an example. The paper also presents some typical performance study scenarios to illustrate the use of the methodology. We hope that the work presented in the paper fuels further research in the area of linking operational specifications and performance modeling. Providing a link between Operational Specification and Performance Modeling will bridge the hitherto existing gap between these two stages of the design process.
There exists a prevalent need of VHDL models for the MOSIS community involved in ASIC design. The accuracy of today's simulations using data book values is not sufficient to provide results comparable to actual chip testing. The technique discussed here describes a method using back annotated data to calculate proper delays based on the input rise and fall times along with the output capacitive loading for each cell. This data, when combined with the generics Tech, Model, Temp, and Vdd, provide the timing formula with the necessary parameters to calculate the delay for each input to each output. This calculation is performed at elaboration time for the models based on those generics. Currently, there are four supported conditions based on Technology, Temperature, Voltage, and Process: Nominal (1 .2u, 25 Celsius, 5.0 volts, TNTP), Best (1 .2u, -55 Celsius, 5.5 volts, FNFP), Worst (l.2u, 140 Celsius, 4.0 volts, SNSP), and Low Voltage (l.2u, 80 Celsius, 2.0 volts, SNSP). The ability to support other conditions is available with future characterization. Proposed plans include support for 0.8 micron technology.
As part of the VHDL standardization activities, an IEEE working group has been created to gather information and put together a proposal for a set of standard VHDL Mathematical Packages that include most oftenly used real and complex elementary functions with floating point real and complex arguments.
A slide presentation on the comparison of timing approaches in VHDL.
Timing hazards are common problems found in logic circuits. A new integrated hazard detection system (HDS) which is implemented in VHDL, is proposed to detect the static, dynamic and function hazards in any logic circuit that is described structurally in VHDL. This system adopts the IEEE VHDL Model Standard Group 1076 - 1164 Nine-Valued Multiple-Valued Logic package. Without any designer-supplied arbitrary input test patterns, the system predicts which input combinations will cause hazards, reports what type of hazards, and provides detailed timing information on the hazards in the combinational logic circuit with fixed gate delays.
VHDL is becoming an industry standard and several IC design houses are looking into integrating VHDL into their design environments. Complete integration of an external hardware description language such as VHDL into an internally developed design flow is a complex task. Most design environments use tools and HDLs which have been developed internally over many years. Tools and design flows based on VHDL need to be developed. Capability to transfer design data between the two HDLs (internal HDL and VHDL) should be provided. Also, the internal tool suite should be enhanced to take advantage of the powerful features offered by VHDL. In addition to providing an internal design flow which uses VHDL, a true and complete VHDL integration should enhance the internal design environment by tapping into the vast potential that VHDL has to offer as a language, and by utilizing the powerful VHDL based tools available in the market today. Only after complete integration is achieved will the main benefits of using VHDL begin to surface. This paper describes how VHDL is being integrated into the internal design environment in three phases at Intel's Multimedia and Supercomputing Components Group (MSCG).
A conceptual graph is a method of storing knowledge. Using this data structure it is possible to store block diagrams, timing specifications, behavioral descriptions, and more. Using conceptual graphs to store the behavioral description of a device it is possible to create a VHDL description of the device in the form of a process model graph. Sentences describing the behavior of a device can be analyzed and put into the form of conceptual graphs. These would then be joined into one graph which would describe the device's overall behavior. This graph would be, in effect, a list of all the actions which the device performs and the conditions under which they operate. It is now possible to use this to create a VHDL behavioral model of the device. Each action performed by the device could be mapped into one or more processes acting upon signals running between those processes. This Process Model Graph (PMG) could then be edited in order to fill in any holes that might be left by the interpreter, and then combined into a VHDL Entity ready for simulation.
A design automation tool that performs extraction on VLSI layouts to generate circuit schematic and VHDL description, is developed in this research. From a layout given in Caltech Intermediate Format, the schematic description in Electronic Design Interface Format (EDIF) is generated. The multi-level extraction process identifies various components of the circuit and prepares the necessary database to represent components and their connectivity. This database is used to generate the EDIF schematic of the circuit. The connectivity among the components is shown by writing the routing for all the signals of the circuit. The ports on each symbol of the schematic have some VHDL attributes associated with them. The VHDL attributes such as portmode and porttype are written with EDIP cell description.
This paper describes VLSI design experience and new design challenges by VHDL in PFU
Three VHDL simulators were evaluated. Different categories of tests were conducted addressing the classic "interpreted" and "compiled" type simulation and related issues, and performance was compared. With a variety of behavioral, structural and mixed-level benchmark designs, we tested the compilation and simulation speed, monitored memory and disk space usage and design capacity of each simulator. We also investigated their debugging and stimulus creation capabilities, user-programmability, full VHDL support capabilities, PC X-window interface support and on-line help features. In this paper, we will present the benchmarks we used, the testing methodology, results obtained and performance analysis. In addition, we will discuss compatibility with leading commercial synthesis tools, accommodation of third party behavioral level hardware models for system simulation, and interfaces with other high-level languages such as C to enable software and hardware co-simulation. Some interesting observations and implications will also be presented. The final part shows a rating scheme we constructed to judge the overall performance of each simulator. In general, as a user, we want to maintain an objective viewpoint and try to avoid biasing throughout the evaluation. The results and findings of this research turned us into an informed consumer and, as a result, led us to a logical and reasonable purchase decision.
Historically, simulation performance has been a key differentiating factor in the EDA marketplace, since it has a direct impact on designer productivity. VHDL simulators are particularly easy to benchmark, since both the input and the results should be independent of the implementation. However, there are a variety of issues that need to be understood to effectively evaluate VHDL simulation performance. Compiled vs. interpreted systems, flexible timing resolution, and signal tracing sensitivity are examples of criteria that are germane to the performance evaluation process. Additionally, it's important that the input data be representative of current and expected future designs. This presentation will discuss the process of evaluating VHDL simulation performance, focusing on a variety of factors which can effect performance.
Large VHDL models can be verified using simulation techniques. Simulations of this sort require extensive computing power and can run for long periods of time. Few machines are available which can execute large simulations in a reasonable time period and they are quite expensive. A worthwhile environment for simulating extremely large VHDL models is to use an existing network of workstations. The Quest project at the University of Cincinnati was originally designed to run large simulations on a specialized hardware box and is currently being ported to run on a network of UNIX workstations. One of the limiting factors in a distributed network environment is communication between simulation objects (which represent VHDL processes in this case). Simulation objects communicate by transferring messages. Objects which reside on a common machine can take advantage of high speed shared memory, while objects residing on different machines rely on network communications. A communication system has been developed to run on a network of SCI or SUN workstations at Wright Patterson Air Force base. Workstations contain between one and four processors, and are connected with Ethernet. The communication system has been designed to take advantage of both shared memory (within a workstation) and Ethernet (between workstations) to facilitate the transfer of information between simulation objects. The system has also been designed to take advantage of SCRAMNet (a ring of memory expansion cards, connected with fiber optic links to emulate shared memory between machines) networks which may exist between selected workstations to speed up inter-machine communications. The simulator does not require ordered delivery of messages and to date our system does not address this issue (messages are not guaranteed to be ordered). This allows the communication system to be fast. We plan to study the impact of ordering messages based on simulation time (we expect the simulation time to improve, even though the message passing system will be slower). Another interesting aspect of the design is that migration of simulation objects will be implemented. Thus as computing power is needed, long running simulations can temporarily move off selected workstations. As computing power becomes available, a simulation can take advantage of the free resources (by migrating simulation objects on to different workstations) and reduce the simulation execution time.
As VHDL grows in popularity, larger and larger models are designed in VHDL, requiring considerable system resources for simulation. A simulation's demand for resources can easily overload a single system in terms of processor power, physical memory, and disk space. A method of dealing with this problem is to design a simulator which uses the capabilities of a multiple-instruction multiple-data (MIMD) machine. This has been accomplished at the University of Cincinnati through the QUEST project on the ES-Kit, a MIMD machine with 16 Motorola 88000-based nodes [1]. However, the ES-Kit is not generally available and we are therefore modifying the QUEST simulator to run on a network of UNIX workstations. The current design runs on a network of Silicon Graphics or SUN workstations. VHDL code is first processed by the Vantage compiler to produce a parsed tree in Vantage Intermediate Format (VIF). The VIF is then analyzed for (i) optimization information, (ii) processor assignment, and (iii) code generation (producing C++). The generated code uses an optimized version of the apE flux communication layer to manage communication across one of three communication layers (shared memory, a hardware supported high speed inter-workstation shared memory called SCRAMNET, and ethernet). At present, many of the known optimizations to Time Warp have been incorporated as compile time switches into the simulator and new optimizations are also being implemented. For example, we have developed and are implementing rollback relaxation [3] and an efficient implementation of lazy reevaluation [2]. The communication support system is also being modified to sort the message queues in timestamp order and also to accelerate the delivery of antimessages. As part of this implementation we are also working to develop an efficient marking strategy for preempted transactions (a problem aggravated by the out of order message delivery possible in the current communication subsystem).
VHDL testbench creation is considered a tedious task which should be automated as much as possible. For each low level VHDL module, no matter which level of abstraction it is, the designer needs to verify that it behaves properly. In addition, for each higher level module which has sub-modules in it, the designer needs to verify its functionality. As the target system gets more complex, with several level of hierarchies, there are more chances to find bugs in the existing design, even if each low level module works correctly individually. In this case, the designers need to extract part of the system, simulate against it, and trace down to where the problems are. No matter in what situation shown above, it is not practical to feed in vectors by hand at the simulation run time. Creating a VHDL testbench for a target DUT (Design Under Test) is a typical approach. The designer has more flexibility to deal with input vectors, output results, and the design itself. More importantly, the maintainability of the design testbench will benefit the whole design process a great deal over the long term. However, as the designs get more complex, the creation of a testbench is usually as tough as the design itself. To reduce the effort of VHDL testbench creation is the motivation for this work.
In this talk, a novel approach to test generation for VHDL behavioral models is described. An algorithm called HBTG, Hierarchical Behavioral Test Generator, has been developed and implemented to systematically generate tests for VHDL behavioral models. HBTG accepts the Process Model Graph and the pre-computed tests for the individual processes of the model, from which it hierarchically constructs a test sequence that exercises the model. The construction of the test sequence is automatic provided that the tests for individual processes of the model are available. The test sequence derived is used for simulation of the model. The modeler is thus relieved of the time-consuming problem of developing test benches.
The Waveform and Vector Exchange Specification (WAVES, IEEE standard 1029.1) provides powerful support for concurrent engineering principles as the Industry standard representation for digital stimulus and response for both design and test communities. Although WAVES is a subset of VHDL, no special support for using WAVES in a VHDL environment is defined within the language. The WAVES-VHDL Interface package has been developed to provide a software interface to support the use of WAVES in a VHDL environment.
This presentation relates our experience of integrating WAVES into an existing ASIC design environment. Presented is an introduction to WAVES, our ASIC methodology as related to simulation, the methodology of WAVES integration including its automation, and obstacles encountered.