Verilog Synthesis Interoperability

IEEE PAR 1364.1

SCOPE

To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing IEEE 1364 standard.

PURPOSE:

The purpose of this standard is to define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their designs compliant with this developed standard.

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