Verilog Synthesis Interoperability
Draft Documentation
This is version 2.1, released
March 28, 2002
of the draft documentation.
The Verilog synthesis draft is now in the IEEE standardization
process and cannot
be made publicly available as per IEEE rules. For questions, contact the WG
Chair (jbhasker@cadence.com).
The responses to the ballot can be read
here (updated 9/11/2002).
Latest update of Section 4 (Semantics) from Ken Coffman
ZIPed MS word and RTF document
For reference: A paper by Don Mills entitaled
RTL Coding Styles That Yield Simulation and Synthesis Mismatches
in PDF format.
David Bishop
Last modified: Wed Sep 11 09:44:50 EDT 2002