Subject: Re: [Fwd: Unsigned as default vector type; was Re: too many functions?]
From: Rob Anderson (rob@reawebtech.com)
Date: Thu Dec 19 2002 - 15:57:31 PST
Hi Jim,
Let's move on to a proposal. You want to duplicate ALL
past and future vector functions from 1164 to numeric_std.
You should list the 1164 vector functions and give an overall
one-line justification. Find a second & we put it in the
list. Deciding is the next part.
Farrel was talking about comp.lang.vhdl. It might be good to
poll there, it is one way to get a user vote. I am sure
we could use input, maybe we should invite a confidential
poll?
We are too few...
Let's just say that if there are 2 or more "NAY" votes
on any of our proposals, we should not go ahead with them.
Also if there are 4 or less people it should be concensus.
(is this fair?)
With a small quorem, the percent has to be higher,
statistically, 3 out of 5 has a voting variance of about
2 so it could have a 20-80% real level of support, not much
of a mandate. Too random.
This voting is for putting it in the proposed package, the
balloters only get to vote on the whole thing and will
rubber stamp it. So this is really the important part.
--Rob
Comments below:
Jim Lewis wrote:
> Rob,
> Perhaps we should resolve this one by majority
> vote?
>
> Cheers,
> Jim
>
> -------- Original Message --------
> Subject: Unsigned as default vector type; was Re: too many functions?
> Date: Thu, 19 Dec 2002 11:37:24 -0700
> From: Farrell Ostler <Farrell.Ostler@xilinx.com>
> Organization: Xilinx, Inc.
> To: "Numeric_Std 1076.3" <vhdlsynth@server.eda.org>
> References: <200212181357.gBIDveow000900@mench.mench.com>
>
> If a full complement of operators were available, I
> could imagine wanting to make unsigned the default type I would
> always use unless there were a compelling reason to take
> exception for a particular signal or port. I can visualize some of
> the simplification that Paul alludes to.
>
> BTW, the idea of using unsigned as the default vector type
> comes up now and then on comp.lang.vhdl.
>
> Does anyone know of negative consequences?
>
> Farrell
>
>
> "Paul J. Menchini" wrote:
>
> > Jim and all,
> >
> > >> 1164 recommends std_logic_vector for vector ports and signals,
> >
> > > Perhaps it is time to add unsigned and signed to this list. There is
> > > really no reason it cannot be supported since the language allows type
> > > casting between std_logic_vector and unsigned and signed.
> >
> > I agree with Jim's thought. I have seen so many models that would be so
> > much simpler (as well as adhering more closely to the model's spec.) if
> > the interfaces were in terms of signed and unsigned instead of the raw
> > vector types.
Well we are all in agreement on that, I said the same thing in the next
paragraph. If the type of an interface is "signed" it helps you connect
the component up to the right signals. In the future there will be other
types like that (eg floating point). So 1164 should really say that
vector types on interfaces should be derived from std_logic_vector.
> >
> > Alternatively, if they would just do one conversion coming in, then one
> > on the way out and operate internally with (un)signed....
> >
> > Paul
>
>
>
This archive was generated by hypermail 2b28 : Thu Dec 19 2002 - 15:49:23 PST