Subject: Abstract for DVCon (HDLCon) paper on Numeric_Std
From: Jim Lewis (jim@synthworks.com)
Date: Mon Oct 07 2002 - 16:09:27 PDT
Hi,
Below is my first cut at an abstract for enhancements
to numeric_std. Comments? The final submission date is
Oct 15th. Note, I plan on updating this as we move
along with the proposals.
Cheers,
Jim
====================================================================
Enhancements to VHDL's Arithmetic Package
VHDL has rich capability for doing signed and unsigned math.
Success in using these types depends on understanding the
types and overloading operators provided the package Numeric_Std
(IEEE Standard 1076.3).
Currently enhancements for numeric_std are being worked on/finalized
for the next draft of the standard. These enhancements include,
logical reduction functions for unsigned and signed,
overloaded array/scalar logic operations for unsigned and signed,
overloaded array/scalar addition operations for unsigned and signed,
functions TO_X01, TO_X01Z, TO_UX01, IS_X for unsigned and signed.
This paper will provide details about the new features of Numeric_Std
as well as provide some rules of thumb for remembering the
overloading. This paper be given in a mini-tutorial format to
help those who are not currently using Numeric_Std to make the
transition.
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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