Re: rob_p1 And Ben_P1


Subject: Re: rob_p1 And Ben_P1
From: Jim Lewis (jim@synthworks.com)
Date: Sun Oct 06 2002 - 08:29:11 PDT


> Is there any reason as to why we can't also move the contents of package
> reduce_Pack to std_logic_1164?
Reduction operators for std_logic_vector and std_ulogic_vector are already
proposed for std_logic_1164.

Reduction operators for SIGNED and UNSIGNED can only go in numeric_std.

Jim

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis                        
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~



This archive was generated by hypermail 2b28 : Sun Oct 06 2002 - 08:32:08 PDT