Subject: Re: rob_p1 And Ben_P1
From: VhdlCohen@aol.com
Date: Fri Oct 04 2002 - 12:56:48 PDT
I propose that we move all the std_logic_[u]vector
functions to 1164, and all the SIGNED, UNSIGNED functions
to numeric_std?
Thus in the std_logic_1164 package would include for the std_logic[u]vector:
-- overloaded logical operators
-- vectorized overloaded logical operators
-- vectorized reduce operators <<<<<<<<<<
-- the current conversion functions
The Numeric_Std would include the updated Numeric_std PLUS
all the subprograms in the Numeric_Unsigned.
I would like to discuss some issues:
1. Combining into Numeric_Std the Numeric_Unsigned (operators that treat
std_logic_[u]vector as unsigned) may be unsettling to users who want the
compiler to check that, per their methodologies, std_logic_vector must never
be treated as unsigned. Those designers insist that unsigned arithmetic
require the use of UNSIGNED. Thus, if the Nemric_unsigned is not called with
the "use" statement, the compiler will fail the addition of an
STd_Logic_vector object and an integer.
Our solution would not perform that check. I don't know how to solve this
issue. However, I feel conformable with the proposal because I see no reason
why Std_Logic_[u]vector cannot be treated as unsigned. For sake of argument,
Verilog does!
<1) get 1164 to cover bit_vectors
2) get rid of numeric_bit
I'll go along with that.
Ben
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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