Subject: Re: rob_p1 And Ben_P1
From: VhdlCohen@aol.com
Date: Fri Oct 04 2002 - 11:32:48 PDT
In a message dated 10/4/02 10:53:08 AM Pacific Daylight Time,
rob@reawebtech.com writes:
> <Rob_P1>
> I propose that we move the following match functions
> based on std_ulogic, std_logic_vector, std_ulogic_vector
> to std_logic_1164 (which is also open for modification
> right now).
>
Is there any reason as to why we can't also move the contents of package
reduce_Pack to
std_logic_1164? After alll the std_logic_1164 has all the AND, OR, XOR
functions, and the reduce operators really belong thee.
I propose that we move the contents of package reduce_Pack to
std_logic_1164.
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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