Subject: [Fwd: Re: Support for NUMERIC_UNSIGNED]
From: Rob Anderson (rob@reawebtech.com)
Date: Mon Sep 30 2002 - 16:49:45 PDT
Ben,
I agree with the typecasting complaint, however the complaint is
about verbosity, the semantics are clear but take up too much
room on the page.
Another problem I run into is ambiguity, where the tool does not
know which type of vector to assume. I think that is a problem
when you allow closely related types and more operators. Then you
have type qualifiers.
There seems to be something wrong with the way we are doing designs
when these things are so common. Perhaps the interface ports should
maintain the type. Maybe we are completely wrong to tell people to
only use std_logic_vector types on all ports.
In VHDL the type is supposed to convey the intended use. It would be
nice to solve this problem in a way that promotes the use of types
.
--Rob
VhdlCohen@aol.com wrote:
> I propose that we adopt into the vhdl synthesis interoperability
> document the NUMERIC_UNSIGNED package, or a version of it, since
> implementation will be vendor dependent. A copy of that document can be
> fount at
> http://members.aol.com/vhdlcohen/vhdl/vhdlcode/numeric_more.zip
>
> RATIONALE: Many design use std_logic_vector types for interfaces and
> architectural signals. These design also assume that those objects of
> std_logic_vector types are treated as Unsigned numbers. If that
> package were not use, and only the Numeric_Std package is allowed, then
> users would have to do multiple type conversions. Examples:
> count_std_vector <= Unsigned(count_std_vector) + 1;
> if (To_Integer(Unsigned( count_std_vector)) = 15) then ...
>
> Also if the signal is declared as Numeric Unsigned and the interfaces
> as Std_logic_vector, then you still need type conversions:
> count_std_vector <= Std_Logic_Vector((Count_Unsigned) + 1);
>
> All these conversions clutter the code, and add very little value if all
> std_logic_vectors are treated as Unsigned. However with the
> Numeric_Unsigned, code will read as follows:
> count_std_vector <= count_std_vector + 1;
> if (To_Integer(count_std_vector) = 15) then ...
>
> Note that I do NOT propose the Numeric_Signed because after thinking
> further about it, signed number should be of Numeric_Std.SIGNED, in a
> manner similar to Verilog 2001 that supports SIGNED objects, but treats
> all other array objects as Unsigned.
>
----------------------------------------------------------------------------
> Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
> http://www.vhdlcohen.com/ vhdlcohen@aol.com
> Author of following textbooks:
> * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
> 0-9705394-2-8
> * Component Design by Example ", 2001 isbn 0-9705394-0-1
> * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
> * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
>
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>
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