Subject: Re: J1 through J8, or...
From: Alex Zamfirescu (hxml@pacbell.net)
Date: Fri Aug 16 2002 - 18:43:27 PDT
Rob:
Good idea!
I assume that the discussion on JIM_P1
is over, and that since nobody objected,
we are all in agreement (no vote needed) that
the proposal is sound.
----- Original Message -----
From: "Rob Anderson" <rob@reawebtech.com>
To: <vhdlsynth-pilot@vhdl.org>
Sent: Friday, August 16, 2002 6:21 PM
Subject: J1 through J8, or...
> Pilot group:
>
> I am looking at numeric_std and how to fit Jim's functions,
> I will write them up and put them in the package, hopefully
> with concensus and when Alex (chair) indicates. Then I will
> pass the package to David to put on the web as the revised
> package.
>
> I assume numeric_bit needs the same treatment.
>
>
>
> Two issues:
>
> 1) These are addition and subtraction, and we would expect them in
> the package header as ~A.9 through A.12 for the addition ones, but these
> overlap the original subtraction operators. So, do we bump the
> function numbers, or is there a clever way to interject something:
It would be nice to have the same ID for the old functions.
Having a "bumped" ID for the new ones would also make
easy to relize that the functions are only in the new packege.
Any numbering that will leave the old ones intact would
make it for now. We can change that later if needed.
>
> A.8
> A.8a
> A.8b
> A.8c
>
> Other Ideas?
>
>
> Argument for bumping: If you go to the header to look things up, and they
> are not with the other "+" operators, you won't think they exist.
>
> Argument against bumping: this kind of upsets anything referring to that
> A.nn number. It would be nice if we did not have to do that.
>
> 2) Jim was suggesting before that all the std_logic elements be
> changed to std_ulogic, a fundamental change in the package that
> was not proposed yet and would be a big change.
> The initial new headers per Jim have std_ulogic, eg.
>
> function "+"(L:unsigned; R:std_ulogic) return unsigned;
>
> I assume this was accidental, and these
> should be std_logic unless we do go to the trouble to change
> the base element type.
>
> Here is a sample coding of that function:
>
> function "+"(L:unsigned; R:std_logic) return unsigned;
> constant SIZE: NATURAL := L'LENGTH;
> variable L01 : UNSIGNED(SIZE-1 downto 0);
> variable R01 : UNSIGNED(SIZE-1 downto 0):=(others=>'0');
> begin
> if (L'LENGTH < 1) then return NAU;
> end if;
> if (L01(L01'LEFT)='X') then return L01;
> end if;
> if (R='X') then return r01:=(others=>'X');
Is previous line legal VHDL or just a C influence?
> end if;
> R01(0)=R;
":" before "=" needed
> return ADD_UNSIGNED(L01, R01, '0');
L01 is still 0 here, it has to be L?!
> end "+";
>
> Does this look ok, pilot?
The adder "looks" OK, it needs just a few
"additions" :-)
>
> Cheers, Rob
>
Regards,
Alex Z
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