Subject: Re: CP-007 and CP-008: textio for std_logic_1164
From: Jim Lewis (Jim@synthworks.com)
Date: Wed Feb 19 2003 - 13:23:20 PST
Peter Ashenden wrote:
>>4) For hread, oread, dread read enough characters to
>>fill the array (if enough characters are not present
>>then error). If there are extra characters, throw
>>out the leftmost bits of the extra characters.
>>
>>This means to read a 21 bit hex address, I can simply
>>
>>hread(RB, addr) ;
>>
>>Otherwise to get the same meaning, I need to:
>>variable addr_temp : std_logic_vector(23 downto 0) ;
>>
>>hread(RB, addr_temp) ;
>>addr <= addr_temp(addr'range) ;
>
>
> I would be uncomfortable with throwing away surplus bits silently. How
> about reading sufficient digits to fill the array, and if there are
> extra zero bits throw them away. If any extra bits are non-zero, then
> complain. The rationale is that extra zero bits mean that the value
> read could be represented in a number of bits equal to the array size.
> For example, if we do a hex read into a 5-element vector and read 1F, we
> get three extra 0 bits, but that's ok, since 1F can be represented in
> five bits. On the other hand, if we read 3F, we get 001 as extra bits
> and complain, since 3F needs at least six bits to represent it.
This does exactly what I want with enhanced
error protection.
>>5) TO_STR, TO_HSTR, TO_OSTR, TO_DSTR, ...
>>I would like a set of procedures that convert from a
>>std_logic_vector, std_ulogic_vector to a string value.
>>Very similar in concept to 'image except it works for
>>strings. These functions are currently built into
>>write, hwrite, and owrite. The advantage to providing
>>these separately is that someone using assert or
>>VHDL built-in write can use these conversions to allow
>>the printing of std_logic_vector values.
>>
>>For example:
>>
>>assert (ExpectedVal = ReadVal)
>> report "In ... Expected Value /= Read Value. Expected = " &
>> TO_STR(Expected) & " Read = " & TO_STR(ReadVal))
>> severity error ;
>>
>>Similarly without having the standard assert messages,
>>a quick error message can be dumped to the console:
>>if (ExpectedVal /= ReadVal) then
>> write(OUTPUT, "In ... Expected Value /= Read Value. Expected = " &
>> TO_HSTR(Expected) & " Read = " & TO_HSTR(ReadVal)) ) ;
>> ErrCnt := ErrCnt + 1 ;
>>end if ;
>
>
> This is reminiscent of the Java idea of having a toString function for
> every type. While 'image goes part of the way, it is no overloadable,
> so we can't add parameters for formatting.
>
> Maybe what we could define is textio functions called write that
> parallel the write procedures. The differences would be
>
> - return a string instead of having a line parameter
> - no version with a GOOD parameter
>
> For bit_vector, std_(u)logic_vector, etc, have a version of the write
> procedures and functions that include a BASE parameter. Then you could
> do
>
> report "..." & write(ReadVal, base=>hex);
>
> This does largely what you describe, but integrates more cleanly with
> the existing language framework.
The limitation of 'image is that for std_logic values it
returns a string with the literal in it:
"'1'"
So even if we could extend it, it is of limited usefullness
unless we could fix the above issue.
Overloading write would be potentially confusing. With
this feature I intend to use VHDL's built-in write that
writes directly to a TEXT file. So with an overloaded
write, it would look like:
write(Output, "..." & write(ReadVal, base=>hex)) ;
For hex formatting, I would prefer that we have a
consistent solution. Hence if we are going with
hwrite, I would like something like to_hstring.
If we are also going to implement write(..., base=>hex,...)
I would not mind seeing both.
You made me realize that I forgot to ask for formatting
capability such field width and justification.
write(Output, to_string(now, right, 12) & " " & to_hstring(A_slv)) ;
This to me would work quite well in lieu of printf.
Perhaps in a VHDL sense, it is easier than printf.
Cheers,
Jim
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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