Subject: Re: CP-003
From: Jim Lewis (Jim@synthworks.com)
Date: Wed Feb 19 2003 - 07:38:49 PST
>>For math operators,
>> '1' becomes "000 ...1"
>> '0' becomes "000 ...0"
>>
>>Yes, using arrays with bits does add some non-orthagonality
>>to the operator overloading, but this is engineering and
>>non-orthagonality is a normal part of life.
>
>
> Although not relevant (at this time) would a user expect the
> proposed extension for math operators?
> Signal a : signed (3 downto 0);
> Signal b : unsigned( 3 downto 0);
>
> May be the user expects:
> a and '1' ==> a and "1111" sign extension since a is a signed
> b and '1' ==> b and "0001" since b is an unsigned
> (In 1076.3 for arithmetic operations a +'1' (and b + '1')
> is not supported)
>
> Egbert Molenkamp
I think your comment is very relevant. If a user
to going to be able to manage VHDL's overloading, it
needs to be implemented for all relevant types.
Since 1076.3 already implements logic operators,
I think this would also need to be implemented.
I would expect the understanding of scalar values for logic
operators to be consistent across all types. Hence I
would still expect '1' to be "1111" for signed and
unsigned. A logic operation is a control operation
which is does not consider that numeric sense of the
number.
Cheers,
Jim
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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