Subject: CP-003
From: Jim Lewis (Jim@synthworks.com)
Date: Tue Feb 18 2003 - 17:17:54 PST
VHDL has asked us to know rules about the operators.
For example:
Addition operators:
Size of result = maximum of size of operands.
Multiplication operators:
Size of result = sum of the size of each operand
As experienced VHDL users, we are comfortable with these
rules because we learned them and have used them for some
time. Verilog users complain about these rules all the
time because Verilog does not have these restrictions.
Another example:
Arithmetic operators allow operands to have different sizes.
Logic operators do not allow array operands to have differnt
sizes.
So currently, we have a context understanding of logic
and arithmetic operators. They are already different in
how the allow operands to be used.
For arithmetic it makes sense to understand '1'
as "00000001".
For logic I believe it makes sense to understand a control
bit being '1' as expainding to "11111111". When I did gate
level design, we had libraries with bussed parts. One of
the parts allowed "AND"ing a control bit with a vector.
This is a new rule. It would not be unusual to be uneasy
about it at first. It is not familiar. However, that
alone is not a good reason to reject it.
Bhasker's argument is that if we understand '1' for
arithmetic as "00000001", then understanding '1' for
logic as "11111111" will be confusing. I disagree
with this. With this type of reasoning, we should
not have allowed addition operators to use different
sized operands. But numerics are different from
logic operators. As a result, it is quite reasonable
for addition to use different sized operands as well
as mixing integers and arrays. In an engineers'
world, complete symmetry does not necessarily make
sense.
Complete chaos does not make sense either. As a result,
I agree with Lance's opinion. I would only want these
operators for std_logic_vector and std_ulogic_vector if
I can also have them for bit_vector, unsigned, and
signed. As Steve mentioned earlier, VHDL-200X is
considering fast-tracking items and these are a
candidate.
Without these operators, will be difficult to get people
away from the priority select structure:
Y <= A when ASel = '1' else
B when BSel = '1' else
C when CSel = '1' else ... ;
There is confusion about std_logic_1164 and numeric_std.
This is mainly due to lack of user level documentation.
Cheers,
Jim
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This archive was generated by hypermail 2b28 : Tue Feb 18 2003 - 17:20:29 PST