Subject: Re: re CP-003 vector/scalar logical operators
From: Stephen Bailey (Stephen.Bailey@synopsys.com)
Date: Mon Feb 17 2003 - 10:47:47 PST
> Note that the VHDL-200x process may also consider vector/scalar logical
> operators for bit_vector and bits. If we adopt the status quo (either
> explictly or by default) and VHDL-200x comes up with a clear winner, it
> would make sense for us to subsequently follow suit.
Just to make sure all are aware of the 200x "fast-track" process:
We (the VASG) will decide whether or not to have a fast-track effort next
Thursday (27 Feb). The fact that a language enhancement request impacts a
related standard (such as 1164) is a key factor in determining whether to
consider a request for fast-tracking. (The other factors are relatively
non-controversial and localized/limited LRM impact.) While the VASG does not
require the request to be submitted/known by the 27 Feb meeting, any
fast-tracked items will have a very short turn-around time. Therefore, it is
best if 1164 can come to consensus on this issue as quickly as possible.
The 3 items that are currently candidates for fast-tracking are:
- Unary reduction operators
- Scalar/vector logic operations (which will only be considered if 1164 has
timely consensus)
- Signal spy (cross-module signal referencing, aka XMR in the Verilog world)
If anyone has additional suggestions, please participate in the VASG WG meeting
on 27 Feb or send me an email (privately or to vhdl-200x).
Now, speaking as a member of 1164 and not as chair of 1076, I will defer to Jim
Lewis, David Bishop and other designers as to the preferred resolution. I can
see the desirability of having vector/scalar logical operations, in general
(and, in particular, the original proposal seemed to me to be logical). But, I
will be happy with any resultant consensus driven by user needs and
expectations.
-Steve Bailey
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