Subject: Re: [Fwd: from [Jim Lewis
Jim and all,
I'm thinking about this issue, too. But, one thing struck me:
> -----Forwarded Message-----
> Date: Thu, 30 Jan 2003 18:57:53 -0800
>> I vote to accept all except CP-003. I find this proposal
> Bhasker,
> What you are saying makes sense for arithmetic operators. In fact,
> I will show this with two applications:
> Read-back logic for bus type logic.
> The logic works something like this:
> Y <= (A and ASel) or (B and BSel) ;
> My challenge to you is, propose a hardware and code efficient
> Y <= (A and (A'Range => ASel)) or (B and (B'Range => BSel)) ;
> An alternate solution for this that does work requires intermediate
> vASel <= (others => ASel) ;
No intermediate signals are required:
Y <= (A and (A'range => ASel)) or (B and (B'range => BSel));
> Conditional add/subtract:
> -- subtraction via 1's complement + 1
> Interestingly enough this shows both the logic and the
> Note this is a very detailed implementation that I would
> Y <= A + B when (SubSel = '1') else A - B ;
> Without the new functions, intermediate signals would be required:
> vSubSel <= (others => SubSel) ;
> Y <= A + (B xor vSubSel) + SubSel ;
Ditto:
Y <= A + (B xor (B'range => SubSel)) + SubSel;
> What I am trying to do with this proposal is to simplify some of the
Simplification is always good, as long as it doesn't lead to
> These functions really help with the hardware implications.
If so, then perhaps we can provide them with other names?
Paul
This archive was generated by hypermail 2b28
: Fri Jan 31 2003 - 07:41:33 PST
From: Paul J. Menchini (mench@mench.com)
Date: Fri Jan 31 2003 - 07:39:53 PST
> From: Jim Lewis <synthwrk@easystreet.com>
> To: Std_Logic 1164 <vhdl-std-logic@server.eda.org>
> Cc: Jayaram Bhasker <jbhasker@ieee.org>
> Subject: The logic behind CP-003
> References: <200301310218.h0V2IcS2008944@server.eda.org>
>> non-intuitive. The more common interpretation is to treat '1' as
>> "000...001", rather than "111....111". For example, "A and '1'"
>> would mean "A and "000001"" which is same as "A + '1'" which means
>> "A + "000001"". I therefore reject this proposal.
>>
>> - bhasker
> I would like to convince you to vote otherwise on CP-003.
> we are proposing something similar to the above for +,- in 1076.3.
> On the other hand, for controlling busses (logic),
> applying the bit to the entire array makes sense.
> ===================================
> Resources: ASel, BSel, ... outputs of a decoder
> Busses to be controlled: A, B, ... all arrays.
> signal ASel, BSel : std_logic ;
> signal Y, A, B : std_logic_vector(7 downto 0) ;
> solution that effectively does this. One thing I have tried
> that is not portable to synthesis tools is:
> signals:
> signal vASel, vBSel : std_logic_vector(A'range) ;
> vBSel <= (others => BSel) ;
> Y <= (A and vASel) or (B and vBSel) ;
> ===========================
> signal SubSel : std_logic ; -- 1 = subtract, 0 = Add
> signal Y, A, B : signed(7 downto 0) ;
> Y <= A + (B xor SubSel) + SubSel ;
> arithmetic operation. For "xor SubSel", '1' becomes
> "11111111" and '0' becomes "00000000". For "+ SubSel",
> '1' becomes "00000001" and '0' becomes "00000000".
> prefer not to use, however, sometimes to get good resource
> sharing on synthesis tools this produces more effective
> results than:
> signal vSubSel : std_logic_vector(B'Range) ;
> tricks that are required to get a synthesis effective implementation
> of the above code.
obsfucation.
Counter-intuitiveness (although somewhat in the mind of the intuiter)
can lead to very hard to diagnose errors.