Subject: [Fwd: from [Jim Lewis
-----Forwarded Message-----
Date: Thu, 30 Jan 2003 18:57:53 -0800
> I vote to accept all except CP-003. I find this proposal
Bhasker,
What you are saying makes sense for arithmetic operators. In fact,
I will show this with two applications:
Read-back logic for bus type logic.
The logic works something like this:
Y <= (A and ASel) or (B and BSel) ;
My challenge to you is, propose a hardware and code efficient
Y <= (A and (A'Range => ASel)) or (B and (B'Range => BSel)) ;
An alternate solution for this that does work requires intermediate
vASel <= (others => ASel) ;
Many miss this "trick" and simply code the logic with
Y <= A when ASel = '1' B when BSel = '1' else (others => '0') ;
Sometimes ok for 2:1 and 3:1, but always inferior for 4:1
Conditional add/subtract:
-- subtraction via 1's complement + 1
Interestingly enough this shows both the logic and the
Note this is a very detailed implementation that I would
Y <= A + B when (SubSel = '1') else A - B ;
Without the new functions, intermediate signals would be required:
vSubSel <= (others => SubSel) ;
Y <= A + (B xor vSubSel) + SubSel ;
What I am trying to do with this proposal is to simplify
These functions really help with the hardware implications.
Cheers,
P.S. there is more info in the proposal:
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This archive was generated by hypermail 2b28
: Thu Jan 30 2003 - 19:26:56 PST
From: Peter Ashenden (peter@ashenden.com.au)
Date: Thu Jan 30 2003 - 19:26:20 PST
From: Jim Lewis <synthwrk@easystreet.com>
To: Std_Logic 1164 <vhdl-std-logic@server.eda.org>
Cc: Jayaram Bhasker <jbhasker@ieee.org>
Subject: The logic behind CP-003
References: <200301310218.h0V2IcS2008944@server.eda.org>
> non-intuitive. The more common interpretation is to treat '1' as
> "000...001", rather than "111....111". For example, "A and '1'"
> would mean "A and "000001"" which is same as "A + '1'" which means
> "A + "000001"". I therefore reject this proposal.
>
> - bhasker
I would like to convince you to vote otherwise on CP-003.
we are proposing something similar to the above for +,- in 1076.3.
On the other hand, for controlling busses (logic),
applying the bit to the entire array makes sense.
===================================
Resources: ASel, BSel, ... outputs of a decoder
Busses to be controlled: A, B, ... all arrays.
signal ASel, BSel : std_logic ;
signal Y, A, B : std_logic_vector(7 downto 0) ;
solution that effectively does this. One thing I have tried
that is not portable to synthesis tools is:
signals:
signal vASel, vBSel : std_logic_vector(A'range) ;
vBSel <= (others => BSel) ;
Y <= (A and vASel) or (B and vBSel) ;
inferior priority select logic:
and larger.
===========================
signal SubSel : std_logic ; -- 1 = subtract, 0 = Add
signal Y, A, B : signed(7 downto 0) ;
Y <= A + (B xor SubSel) + SubSel ;
arithmetic operation. For "xor SubSel", '1' becomes
"11111111" and '0' becomes "00000000". For "+ SubSel",
'1' becomes "00000001" and '0' becomes "00000000".
prefer not to use, however, sometimes to get good resource
sharing on synthesis tools this produces more effective
results than:
signal vSubSel : std_logic_vector(B'Range) ;
some of the tricks that are required to get a synthesis
effective implementation of the above code.
Jim
http://www.eda.org/vhdl-std-logic/proposals/CP-003-array-scalar-logical-operators.txt
--
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Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787