Subject: BOUNCE vhdl-std-logic@eda.org: Non-member submission from ["Jayaram Bhasker"
>From petera Thu Jan 30 10:30:14 2003
Peter:
I vote to accept all except CP-003. I find this proposal
- bhasker
------
-----Original Message-----
Dear colleagues,
I'd like to call for a vote on several of the change proposals for
At this stage, I would ask you to vote on each of the following
CP-001 Uncomment xnor operators
CP-002 Add shift operators for vector types
CP-003 Add array/scalar logical operators
CP-004 Add capacitive drive strength
CP-005 Make vector result subtypes same as 1076 operators
CP-006 Add logical reduction operations/operators
CP-009 Provide 'image attribute
CP-010 Add match functions like numeric_std.std_match
For each proposal, you can
If you change your mind during the vote period, I will count the last
For a vote to pass, it will require a return of 75% of voting members,
Please note that only current DASC members are eligible to have their
Please forward your vote to me at peter@ashenden.com.au by 5:00pm US-PST
Thanks for your participation!
Cheers,
Peter Ashenden
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: Thu Jan 30 2003 - 18:20:04 PST
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Subject: RE: Call for vote on P1164 change proposals
Date: Thu, 30 Jan 2003 13:30:05 -0500
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Thread-Topic: Call for vote on P1164 change proposals
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From: "Jayaram Bhasker" <JBhasker@eSilicon.com>
To: "Peter Ashenden" <peter@ashenden.com.au>, <vhdl-std-logic@server.eda.org>
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non-intuitive. The more common interpretation is to treat '1' as
"000...001", rather than "111....111". For example, "A and '1'"
would mean "A and "000001"" which is same as "A + '1'" which means
"A + "000001"". I therefore reject this proposal.
J. Bhasker, eSilicon Corp
1605 N. Cedar Crest Blvd, Ste 615, Allentown, PA 18104
jbhasker@esilicon.com, 610.439.6831, 610.770.9634(fax)
From: Peter Ashenden [mailto:peter@ashenden.com.au]
Sent: Monday, January 27, 2003 8:25 PM
To: vhdl-std-logic@eda.org
Subject: Call for vote on P1164 change proposals
P1164, the VHDL standard logic package. The summary and detailed change
proposals are on the web server at www.eda.org/vhdl-std-logic.
proposals:
(1) vote to accept the analysis and any changes it proposes, or
(2) vote to reject the analysis, citing reasons and revisions to make
the analysis acceptable
(3) abstain
vote received from you. I will acknowledge votes by reply email.
less than 30% abstentions, and 75% those votes that accept or reject to
be accept votes. (These rules mirror the rules for sponsor ballot.)
vote recognized. For this ballot, I will also collect votes from
non-DASC-members and tally them separately for information.
Friday 14 February 2003. Please also indicate whether you are a DASC
member. (If you want to join up, see www.dasc.org for details.)
P1164 Chair
--
Dr. Peter J. Ashenden peter@ashenden.com.au
Ashenden Designs Pty. Ltd. www.ashenden.com.au
PO Box 640 Ph: +61 8 8339 7532
Stirling, SA 5152 Fax: +61 8 8339 2616
Australia Mobile: +61 414 70 9106