Subject: Re: match functions
From: David Bishop (david.bishop@kodak.com)
Date: Thu Dec 12 2002 - 10:22:08 PST
John Michael Williams wrote:
>
> Hi All.
>
> I think it would be a serious error to add functions of
> the same name (and signature) to more than one package.
That's not what's happening here though.
> It seems a bit bizarre that two WG's would be
> in sort of a competition to add functions to their
> packages. Something should be worked out so
> that the PURPOSE of the new function would determine
> the package in which it was located.
Lets go over a little history here....
Long ago (1993) I put a series of funcitons which got to be named
"std_match" into numeric_std. These functions allows for the 1164
"-" to be use as a "match anything" and the "L" and "H" values in
1164 to match the "0" and "1" respectively. The "=" in 1164 did not
allow for this.
In numeric_std (1076.3) we created functions for "std_ulogic",
"std_logic_vector" and "std_ulogic_vector" as well
as "signed" and "unsigned" as you can see at:
http://vhdl.org/vhdlsynth/vhdl/numeric_std.vhd
The plan here is to create a new function called "match" in 1164
which would do a "std_match" for "std_ulogic", "std_logic_vector"
and "std_ulogic_vector" based on the table for "std_match" in
the numeric_std package. You would actually copy the table into
std_logic_1164 from numeric_std
> If there is a logic-state meaning, 1164 should
> add the function; if there is a computational
> meaning, numeric-std.
Agreed. Unfortunately this got overlooked when 1164 was originally
published.
The new "match" functions in 1076.3 (numeric_std) would only
be for the "signed" and "unsigned" types.
> It isn't much of a bother to USE a package just to get
> one function; it would be a problem if the tool(s) involved
> couldn't handle anything but USE (package_name).ALL,
> and this resulted in exposure of two functions
> of the same name.
You said it. That's why we changed the name from "std_match" to "match"
in 1164, so it would not conflict with the existing 1076.3 package.
When all is said and done, "std_match" will still work (from the numeric_std
package). If you use "signed" and "unsigned" (which you get from
the 1076.3 numeric_std package), then the new "match" routines which I
am proposing would overload for those types only. For a std_ulogic
type or subtype it would come from std_logic_1164.
example:
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- assuming the new versions of both specs
architecture xxx of yyy is
signal slv1, slv2 : std_ulogic_vector (15 downto 0);
signal us1, us2 : unsigned (15 downto 0);
signal b1, b2, b3, b4 : boolean;
begin
b1 <= std_match ( slv1, slv2 ); -- comes out of "numeric_std"
-- (could be an alias to "match" in 1164)
b2 <= std_match (us1, us2); -- comes out of "numeric_std"
b3 <= match (slv1, slv2 ); -- comes out of 1164
b4 <= match (us1, us2); -- comes out of "numeric_std".
-- David W. Bishop dbishop@vhdl.org
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