Subject: Re: CP-010 in address decoding
From: Farrell Ostler (Farrell.Ostler@xilinx.com)
Date: Mon Dec 09 2002 - 13:55:41 PST
By making a small simplification to the Match
function vis-a-vis the Std_Match function,
the address decoding example would work
for limiting case of MAB = AB. The decoding example is
illustrative of how such limiting cases arise from time to
time in practice.
The simplification is to remove the first IF
statement:
> IF ((l'LENGTH < 1) OR (r'LENGTH < 1)) THEN
> ASSERT FALSE
> REPORT "STD_LOGIC_1164.MATCH: null detected, returning FALSE"
> SEVERITY WARNING;
> RETURN FALSE;
> END IF;
Then, instead of regarding null arguments as error conditions,
the function allows them and returns the appropriate
result.
Farrell Ostler
Jim Lewis wrote:
> Farrell,
> The issue is not the match function itself.
> Historically std_match was implemented in numeric_std
> for sul, slv, and sulv. Going forward, it would be
> nice to have the std_match function which overloads
> sul, slv, and sulv in std_logic_1164.
>
> The issue is if we move it from one to the other,
> it may break some code (because it is correct to call
> the match function by numeric_std.std_match(...))
>
> So now we really don't want to break code. How
> do we do it? CP-010 suggests using a new function
> named match.
>
> This opens a new issue. For going forward it would
> be nice if everyone called match the same name. Hence,
> perhaps we should put match in numeric_std (which is
> also open).
>
> Based on your example, perhaps we should be
> considering two types of match functions. One
> that returns boolean and one that returns std_logic.
>
> SEL <= '1' when match(A(0 to AB-MAB-1), "1101...01")
> else '0';
>
> SEL <= EQUAL(A(0 to AB-MAB-1), "1101...01") ;
>
> I tenatively gave the one which returns std_logic
> a different name. I suspect this may be necessary
> to avoid overloading issues. However we may also
> want to consider the possibility of equal being
> match.
>
> Cheers,
> Jim Lewis
>
> Farrell Ostler wrote:
> > Let AB be the number of address bits in a system.
> > A memory is to be mapped into this space with the address size
> > of the memory variable up to AB, in which case the memory would
> > occupy the entire address space. (The actual size of the
> > memory would be determined at elaboration when the system
> > generics are evaluated.)
> >
> > The match function is an attractive primitive for doing the
> > address decoding for the memory's select signal. Here are
> > two reasons:
> >
> > 1. Match won't generate simulation warnings during the period of time
> > from simulation start until the system address gets initialized
> > out of the 'U' state, as happens, for example, with the overloaded
> > "=" operator in numeric_std.
> >
> > 2. If there is a desire to economize the address decoding at the
> > expense of aliasing the memory in a larger address range, the
> > "match on don't care" behavior caters nicely.
> >
> > Let MAB be the number of address bits that the memory actually
> > needs, let A: std_logic_vector(0 to AB-1) be the system
> > address signal and let SEL: std_logic be the memory select signal.
> > Then, the decoding could be done as, e.g.,
> >
> > SEL <= '1' when match(A(0 to AB-MAB-1), "1101...01")
> > else '0';
> >
> > The address decoder would work fine for all MAB < AB
> > but then fail when MAB = AB, although this later case is a perfectly
> > valid system.
> >
> > Farrell Ostler
> > Xilinx
> >
> > P.S. For reference, I have copied the proposed match implementation,
> > below.
> >
> >
> > FUNCTION match ( l, r : std_logic_vector ) RETURN BOOLEAN IS
> > ALIAS lv : std_logic_vector(1 TO l'LENGTH) IS l;
> > ALIAS rv : std_logic_vector(1 TO r'LENGTH) IS r;
> > BEGIN
> > IF ((l'LENGTH < 1) OR (r'LENGTH < 1)) THEN
> > ASSERT FALSE
> > REPORT "STD_LOGIC_1164.MATCH: null detected, returning FALSE"
> > SEVERITY WARNING;
> > RETURN FALSE;
> > END IF;
> > IF lv'LENGTH /= rv'LENGTH THEN
> > ASSERT FALSE
> > REPORT "STD_LOGIC_1164.MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
> > SEVERITY WARNING;
> > RETURN FALSE;
> > ELSE
> > FOR i IN lv'LOW TO lv'HIGH LOOP
> > IF NOT (match_table(lv(i), rv(i))) THEN
> > RETURN FALSE;
> > END IF;
> > END LOOP;
> > RETURN TRUE;
> > END IF;
> > END match;
> >
> >
>
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Jim Lewis
> Director of Training mailto:Jim@SynthWorks.com
> SynthWorks Design Inc. http://www.SynthWorks.com
> 1-503-590-4787
>
> Expert VHDL Training for Hardware Design and Verification
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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