Subject: CP-006: Add logical reduction operations/operators
From: Stephen Bailey (Stephen.Bailey@synopsys.com)
Date: Mon Dec 09 2002 - 11:20:13 PST
The proposed function names will create homographs for any code that also
uses Synopsys's std_logic_misc package. While this is not an IEEE standard
package, there are a relatively large number of designs that use this
package.
Also, it seems that the VHDL community is forever stuck on choosing the
longest names possible! A habit that I would like to see broken as long as
we don't digress into code obfuscation.
Therefore, I suggest that the names of the functions be changed to
<logical-op>r as the example code in the detail section of the change
proposal uses (e.g., xorr, orr, andr, etc). Regardless of the names chosen
(and their length ;-), I do think we need to avoid homographs with
std_logic_misc.
Hopefully, 1076 will be modified in the not-too-distant future to provide
unary reduction operators in the language which 1164 can then overload, if
needed.
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Stephen Bailey
Staff Corporate Applications Engineer, VHDL Simulation
Synopsys Inc.
sbailey@synopsys.com
303-775-1655 (voice/mobile)
650-584-4893 (corporate voice mail)
Read Verification Avenue:
http://www.synopsys.com/va
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