Subject: Re: std_logic_1164: CP-010 and numeric_std:Rob_P1
From: Peter Ashenden (peter@ashenden.com.au)
Date: Fri Dec 06 2002 - 21:56:14 PST
Jim,
The problem with _moving_ the std_match functions from numeric_std to
std_logic_1164 is that models that refer to numeric_std.std_match
(either with selected names or via a use clause) would break.
The problem with _copying_ the functions to std_logic_1164 is that you
would then have homographs in the two packages, and models that use (in
the use clause sense) both packages and refer to std_match would break.
Hence my proposal to call the functions in std_logic_1164 match instead
of std_match. You could add match as an alias for std_match in
numeric_std if you want consistency of naming across the packages for
new models.
Cheers,
PA
On Sat, 2002-12-07 at 13:01, Jim Lewis wrote:
> CP-010 Analyzed Add match functions like numeric_std.std_match
> http://www.eda.org/vhdl-std-logic/proposals/CP-010-match-functions.txt
>
> In numeric_std, it was proposed in proposal Rob_P1/P2
> (http://www.eda.org/vhdlsynth/pilot/hm/0026.html), that
> the std_match functions for std_ulogic, std_logic_vector, and
> std_ulogic_vector be moved to std_logic_1164.
>
> This would satisify CP-010 and Rob_P2. Is this a move that
> everyone would support? Otherwise, CP-010 proposes adding a match
> function to std_logic_1164. This means that we should add a
> match function to numeric_std. There is more meaning to a
> function when it is globally used.
>
> Cheers,
> Jim
>
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Jim Lewis
> Director of Training mailto:Jim@SynthWorks.com
> SynthWorks Design Inc. http://www.SynthWorks.com
> 1-503-590-4787
>
> Expert VHDL Training for Hardware Design and Verification
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-- Dr. Peter J. Ashenden peter@ashenden.com.au Ashenden Designs Pty. Ltd. www.ashenden.com.au PO Box 640 Ph: +61 8 8339 7532 Stirling, SA 5152 Fax: +61 8 8339 2616 Australia Mobile: +61 414 70 9106
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