RE CP 008 Formated IO

Subject: RE CP 008 Formated IO
From: Jim Lewis (jim@synthworks.com)
Date: Fri Dec 06 2002 - 17:54:18 PST

In CP-008, the format for reads and writes proposed are:

   type REPRESENTATION is ( any, binary, octal, hexadecimal );
   procedure READ( L: inout LINE; VALUE out std_logic;
                      GOOD: out BOOLEAN; R: in REPRESENTATION := any );
   procedure WRITE( L: inout LINE; VALUE in std_logic;
                        JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH:= 0;
                        R: in REPRESENTATION := any);

It also suggests that we do not need formatted reads.

I have used both hexidecimal reads and write. The current package
that supports these does have some limitations if the hexidecimal
value is not a multiple of 4. This is what I would like
to see for formatted IO (until we have printf):

   procedure HREAD( L: inout LINE; VALUE out std_logic_vector);
   procedure HREAD( L: inout LINE; VALUE out std_logic_vector;
                      GOOD: out BOOLEAN);
   procedure OREAD( L: inout LINE; VALUE out std_logic);
   procedure OREAD( L: inout LINE; VALUE out std_logic;
                      LENGTH: in Natural := 0);
   procedure HWRITE( L: inout LINE; VALUE in std_logic_vector;
                   JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH:= 0);
   procedure OWRITE( L: inout LINE; VALUE in std_logic_vector;
                  JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH:= 0);

Size of object read shall be equal to the size of VALUE.
If the size of value is not a multiple of 4, the extra bits
of the left most hexidecimal character shall be thrown away.

Size of object written shall be equal to the size of VALUE.
If the size of value is not a multiple of 4, the extra bits
of the left most values of a std_logic_vector, std_ulogic_vector,
and unsigned shall be '0'. The left most values of a signed
value shall match the value of the sign bit.

Cheers,
Jim 

-- 
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Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
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