[Fwd: BOUNCE vhdl-std-logic@eda.org: Non-member submission from [John Willis <jwillis@ftlsys.com>]]


Subject: [Fwd: BOUNCE vhdl-std-logic@eda.org: Non-member submission from [John Willis ]]
From: Peter Ashenden (peter@ashenden.com.au)
Date: Sun Feb 24 2002 - 17:34:29 PST


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Date: Sun, 24 Feb 2002 16:05:29 +0000
From: John Willis <jwillis@ftlsys.com>
Organization: FTL Systems
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To: John Michael Williams <jwill@AstraGate.net>
CC: Std_Logic 1164 <vhdl-std-logic@server.eda.org>,
   "Numeric_Std 1076.3" <vhdlsynth@server.eda.org>
Subject: Re: Precision of Arithmetic
References: <3C7545BF.D83E5481@SynthWorks.com> <3C77EDA7.52B2E534@AstraGate.net>
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John,

Responding as a vendor, there is a great deal of
interest in 64-bit designs out there. The Pentium-
derived processors are some of the last platforms
to hit 64 bit (with the IA64 family). Even these
do a reasonably good job emulating 64 bit. Power
2-4, UltraSPARC and PA-RISC 2.0 have all been 64
bit for several years.

If you're running into a tool implementation limit
there are several leading-edge firms who already
support 64 or 128 bit integers. Stop by at DATE
or DAC and we'd be glad to tell you about one in
particular... GigaSim(TM).

Best regards, John

John Michael Williams wrote:
>
> Hi All.
>
> Is there any interest at present in extending
> integers to, say, 64 bits?
>
> I have run into the 32-bit limit in DSP-related
> functions, and I would guess that address generation
> also would be a problem for newer 64-bit devices
> such as microprocessors.
>
> The synthesizer should be doing the work of
> breaking down wide busses; the designer should not
> have to put segmentation into the code.
> --
> John
> jwill@AstraGate.net
> John Michael Williams

-- 
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John Willis jwillis@ftlsys.com

FTL Systems UK Limited FTL Systems, Inc.

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Company Information: http://www.ftlsystems.com

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