Subject: RE: Ben's Proposal to add reduction operators to Numeric_Std
From: Jayaram Bhasker (jbhasker@cadence.com)
Date: Thu Feb 21 2002 - 11:43:01 PST
This was one of the feedback we received during the 1076.3 ballot, amongst many
others that we decided to postpone for a future release. Someone ought to look at the
past ballot comments for other good ideas for inclusion ...
- bhasker
-----Original Message-----
From: Jim Lewis [mailto:jim@synthworks.com]
Sent: Thursday, February 21, 2002 2:09 PM
To: Numeric_Std 1076.3; Std_Logic 1164
Subject: Ben's Proposal to add reduction operators to Numeric_Std
I support Ben's proposal to add reduction operators to Numeric_Std
and 1164 if both groups add them. Currently I think 1164 is holding
off considering this to wait and see if the language is going to do
this. I am not convinced we should wait for 200X.
First lets assume that xor reduction gets built into the language
and we over load the existing binary xor operator to allow xor
reduction:
signal ParityOut, ParityIn : std_logic ;
signal Data : std_logic_vector(7 downto 0) ;
. . .
ParityOut <= xor Data ;
Ok so this works, but consider the following potentially equivalent
expressions. Note, I am anticipating that a unary usage of xor has
higher precedence than a binary xor.
ParityOut <= ParityIn xor xor Data ;
ParityOut <= ParityIn xor (xor Data) ;
ParityOut <= ParityIn xor xor (Data) ;
ParityOut <= xor Data xor ParityIn ;
ParityOut <= (xor Data) xor ParityIn ;
ParityOut <= xor (Data) xor ParityIn ;
I can read and write this today, but walk away and pick it up
again in 6 months and I have to think about it too much.
Now consider using an xor_reduce function:
ParityOut <= xor_reduce(Data) ;
ParityOut <= ParityIn xor xor_reduce(Data) ;
ParityOut <= xor_reduce(Data) xor ParityIn ;
If the language were to later build in xor_reduce what are the
consequences?
The function declaration would need to change,
from: function xor_reduce ( ...
to: function "xor_reduce" ( ...
Is it legal to overload a predefined operator without using
double quotes around it (assuming I do not conflict with other
overloading)? If it is, the decision should be easy.
1) Create reduction operators now.
2) If the language overloads the operators later, on the next
revision of 1076.3 and 1164, add double quotes around the
overloaded operators and enjoy the benefits of not having
the extra parentheses.
Cheers,
Jim
-----Original Message-----
From: VhdlCohen@aol.com [mailto:VhdlCohen@aol.com]
Sent: Wednesday, January 23, 2002 2:14 PM
To: Jayaram Bhasker; mench@mench.com; peter@ashenden.com.au
Cc: siwg@eda.org
Subject: Numeric_Unsigned/Signed/Extra suggestions for next packages
FUNCTION and_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : SIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
FUNCTION and_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : UNSIGNED) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
--
In addition, need to create Numeric_Unsigned, and NUmeric_Signed
packages that are similar to the Numeric_Std for operations on
Std_Logic_VEctor treasted as Unsigned or Signed numbers. Similar
functions as above need to also be defined for std_logic_vector.
Ben
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
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* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
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