Minutes of meeting of P1164 Working Group, 27 February 2001

at NEC, 2880 Scott Blvd, Santa Clara, CA


Present:

Peter Ashenden (Chair), peter@ashenden.com.au
Paul Menchini, mench@mench.com
Pat Bryant, pbryant@innoveda.com
John Michael Williams, jwill@astragate.net
Bob Myers, rjmyers@raytheon.com
Wolfgang Roethig, wroethig@el.nec.com
Gabe Moretti, gabe@dimensional.com


For information, EIAJ is now JEITA.

Kaba to forward multiple strength proposal material.
(Also check web site).
- need to see if still necessary
- will SDF and VITAL buy in?

Paul proposed to do a quick revision with simple-to-add issues.
- seek input on controversial issues
- seek input on enhancements

Currently working on a 4-yr PAR to end of 2004.

Attend to website on eda.org
- and email list

Easy list (end of 2001)
- std_logic_io
- formatted read/write (radix based)
- range of return values of overloaded logical operators on vector
  types (needs study)

Hard list (later)
- extra strength values

Defer pending coord with other working group
- shift operators on vector types (numeric_std coordination)
  [note from DASC steering cttee: can be moved to easy, since
  numeric_std defined these for signed/unsigned, not for
  std_logic_vector.]
- reduction operators (with 1076-200x)
- 'image for vector types (defer to 1076-200x for all types)

Schedule
- proposal by DAC
- for end of year ballot

Action
- Peter & Paul to draft proposals, for review of reflecter
- Paul to set up reflecter (initial membership from attendance list)
- Post to comp.lang.vhdl, etc to advertise & solicit input