IEEE Standard 1164, Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164), describes the VHDL data types used to model signals with strong, weak, high-impedence and unknown values. It forms the basis for other VHDL standards for RTL synthesis and ASIC library models.
The standard was affirmed in 1993 and, according to IEEE rules, is now due for reaffirmation or revision. A number of proposals have been made for revision, and these have been prioritized for immediate implementation or subsequent evaluation. The P1164 Working Group is developing these proposals into a draft standard. Work items include developing and testing revisions to the standard VHDL packages, developing revisions to the standard document, and evaluating the draft standard in design scenarios. It is expected that work on the proposals selected for immediate implementation be completed and the draft be ready for ballot by early 2003.
Participation is open to all interested parties. Voting membership of the Working Group requires DASC membership. Non-DASC members are invited to participate as observers.