library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity unitdelay is
  generic(wl : positive := 8; async_reset : boolean := true);
  port( clk : in  std_logic;
        rst : in  std_logic := '0';
        ce  : in  std_logic := '1';
        i   : in  std_logic_vector((wl-1) downto 0);
        o   : out std_logic_vector((wl-1) downto 0)
       );
end entity unitdelay;

architecture rtl of unitdelay is

signal wo : std_logic_vector(o'range) := (others => '0');

begin

o <= wo;

G_T_ARST : if (async_reset = true)
  generate
    signal qo : std_logic_vector(o'range) := (others => '0');
    begin
      wo <= qo;
      
      P1 : process(clk,rst) is
        begin
          if (rst = '1') then
              qo <= (others => '0');
          elsif rising_edge(clk) then
            if (ce = '1') then
                qo <= i;
            end if;
          end if;
      end process P1;
end generate G_T_ARST;

G_F_ARST : if (async_reset = false)
  generate
    signal qo : std_logic_vector(o'range) := (others => '0');
    begin
      wo <= qo;
      
      P1 : process(clk) is
        begin
          if rising_edge(clk) then
             if (rst =  '1') then
                 qo <= (others => '0');
             else
               if (ce = '1') then
                   qo <= i;
               end if;
             end if;
          end if;
      end process P1;
end generate G_F_ARST;

end architecture rtl;

configuration cfg_unitdelay of unitdelay is for rtl

  end for;
end configuration cfg_unitdelay;