library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_funny is

-- Declarations for conversion functions.
function std_logic_to_BIT(arg : in std_logic) return BIT;
function BIT_to_std_logic(arg : in BIT) return std_logic;

end CONV_PACK_funny;

package body CONV_PACK_funny is
   
   -- std_logic to enum type function
   function std_logic_to_BIT(arg : in std_logic) return BIT is
   -- synopsys built_in SYN_FEED_THRU;
   begin
      case arg is
         when '0' => return '0';
         when '1' => return '1';
         when others => assert FALSE -- this should not happen.
               report "un-convertible value"
               severity warning;
               return '0';
      end case;
   end;
   
   -- enum type to std_logic function
   function BIT_to_std_logic(arg : in BIT) return std_logic is
   -- synopsys built_in SYN_FEED_THRU;
   begin
      case arg is
         when '0' => return '0';
         when '1' => return '1';
         when others => assert FALSE -- this should not happen.
               report "un-convertible value"
               severity warning;
               return '0';
      end case;
   end;

end CONV_PACK_funny;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_funny.all;

entity funny is

   port( a : in BIT;  y, z : out BIT);

end funny;

architecture SYN_test of funny is

   component IV
      port( A : in std_logic;  Z : out std_logic);
   end component;
   
   signal z_port, y_port : std_logic;

begin
   y_port <= BIT_to_std_logic(a);
   y <= std_logic_to_BIT(y_port);
   z <= std_logic_to_BIT(z_port);
   
   U7 : IV port map( A => y_port, Z => z_port);

end SYN_test;