VASG is responsible for maintaining and extending the VHDL standard (IEEE 1076).    Currently VASG collaborating with the Accellera VHDL TSC to accomplish this task. More on the VASG and Accellera relationship is here.    VHDL is an IEEE/IEC dual-logo standard and VASG coordinates revisions with IEC TC 93. More on IEC TC 93 is here.   

Enhancement Request  

Report a BUG on an IEEE VHDL revision  

Report a BUG on an Accellera VHDL revision  

VHDL standards are available through IEEE Standards associations webpages. To find them, search on VHDL at http://shop.ieee.org.   Note that IEEE currently lists VHDL standards by their IEC numbering.

IEEE Standard Number	IEC Standard Number	IEC Title
1076-2002	61691-1-1: 2004	Behavioural languages--Part 1: VHDL language reference manual
1076.4-2000 VITAL	61691-5: 2004	Behavioural languages: Part 5: VITAL ASIC (application specific integrated circuit) modeling specification
1076.6-2004	62050-2005	VHDL Register Transfer Level (RTL) Synthesis
Note that IEC and IEEE standards are the same except for front matter, titles, and appendicies.

VHDL + VHPI = PAR P1076C = targeted to be IEEE 1076-2006
The IEEE VHPI team finished the work in early 2006. Kudos to Accellera for funding the LRM editing. Became an Accellera standard on June 28, 2006. Currently it is working its way through IEEE standardization.

IEEE VHDL-200X + Accellera Additions
The IEEE VASG started the work in early 2003 as VHDL-200X. The Accellera VHDL Technical Subcommittee took over the work in 2005, funded its technical editing, and did super-human work to finalize it. Became an Accellera standard at DAC 2006 (late July). These language extensions and productivity enhancements are standardized for industry adoption. Currently we expect that this version will be standardized by IEEE sometime in 2007. The delay in standardization is intended to give EDA vendors and users time to try out the new features and perhaps tune them up before IEEE standardization.

Accellera 2007 Revision
Current items being worked include constrained random, coverage, OO, interfaces, and verification data structures (associative arrays, memories, ...)

Join us and help create the next VHDL standards. For details see participation below.

VASG is responsible for maintaining and extending the VHDL standard (IEEE 1076).   Currently VASG collaborating with the Accellera VHDL TC to accomplish this task. 

In this relationship, VASG is responsible for screening enhancement requests via the ISAC.  Bug fixes are proposed directly by ISAC.  Enhancements requests are forwarded to the Accellera VHDL TC. 

The Accellera VHDL TC is responsible for the majority of the revision effort. This includes prioritizing enhancement requests, proposing enhancements, and making sure the enhancements and bug fixes get integrated into the VHDL standard.

When the Accellera VHDL TC has completed and approved draft, they forward the draft to the VASG who then completes the IEEE standardization process for the draft. Hopefully we will see these features around DAC 2007.

Both VASG and the Accellera VHDL TC welcome participation from any person with a vested interest in VHDL. While paying membership in these organizations is not required, it does help fund the standard (typically indirectly). In addition, to have a full "voting" membership, you must be a paying member.

More information on participating in the Accellera VHDL TC is here.

Much of the work and communication of VASG is done via the email reflector.  To join, send an email message majordomo@eda.org with subscribe vhdl-200x in the message body (or use the link below).  You must join the reflector before you can post to it.

Archive           

To be a full "voting" member VASG, you must be a paying member of DASC. To maintain your voting membership you must vote in 2 of 3 votes.

Prior our collaboration with Accellera there was much work done under IEEE. The webpages for that work can be found at:

     Old VASG Page

     Old VHDL-200X Page