Sources:

  [1] PCI Local Bus Specification - Revision 2.2
    -- http://www.pcisig.com
  [2] PCI System Architecture, 3rd Edition. 
    -- Tom Shanley and Don Anderson

  [3] PCI Hardware & Software, Architecture & Design. 
    -- Edward Solari and George Willse

General:

  PCI compliant devices can behave as master or target agents, or
  target agents only. The required pins of a PCI agent include
    o Interface Controls FRAME#, TRDY#, IRDY#, STOP#, DEVSEL#, and
      IDSEL (input), 
    o Error Lines PERR# and SERR#
    o Arbitration Lines REQ# (output) and ACK# (input), 
    o Clock/Reset CLK and RST# inputs, 
    o 32 bit wide Address/Data bus (AD),
    o 4 bit wide Command/Byte Enable line (C/BE).
  There are also numerous optional signals. The Interface Signals are
  `asserted' by holding them low.

Specifications:

  -------- [1] 3.6.1 (pg. 88-89) 

      A target must assert DEVSEL# before any other response 
      within 1 to 3 clocks following the address phase.
  
      (Note: If no target responds, a Master Abort should be 
       performed after 15 cycles)

  -------- [2] pg. 151 (also Spec: 3.2.2.1 pg. 28)

     If the initiator asserts byte-enables of lesser 
     significance than indicated by AD[1:0] the target must 
     terminate the transaction with target abort.

  -------- [2] pg. 131

     During read transactions, the addressed target must
     keep TRDY# deasserted for one extra cycle during
     turnaround cycles.

  -------- [1] 3.3.3.2.1 rule 4 (pg. 53)

     Once a target has asserted TRDY# or STOP# it cannot
     change DEVSEL#, TRDY#, or STOP# until the current data
     phase completes.

  -------- [1] 3.6.1 (pg. 88)

     Once DEVSEL# has been asserted, it cannot be deasserted
     until the last data phase has been completed, except to
     signal Target-Abort.
    
  -------- [1] Appendix C item 25 (pg. 254)

     All targets are required to complete the initial data
     phase of a transaction (read or write) within 16 cycles
     from the assertion of FRAME#.

  -------- [1] 3.2.4 (pg. 39)

     PERR# has a turnaround cycle on the 4th clock after the
     last data phase, which is three clocks after the
     turnaround for AD# lines.

  -------- Spec: 3.3.3.1 rule 4 (pg. 51)

    Once a master has asserted IRDY#, it cannot change IRDY#
    or FRAME# until the current data phase completes. (Note:
    DEVSEL# and IRDY# can go low in either order.)

  -------- Spec: 3.5.4.1 (pg. 81)

    A master is required to assert its IRDY# within 8 clocks
    from any given data phase (initial and subsequent).

  -------- SA pg. 121

    For a Special Cycle transaction, if the initiator
    inserted one or more wait states before asserting IRDY#
    with the message, the master must extend the master
    abort time-out period by at least the same number of
    wait states.

Notes:

  An "address phase" is marked by FRAME# fall; 

  A "data phase" is indicated when TRDY# and IRDY# are high; 

  An "i/o cycle" is a data phase in which the C/BE line indicates an
  i/o read or write;

  From [3] (pg 50-51): 

    After FRAME# has been asserted a target can claim the access cycle
    by asserting DEVSEL#; a "target abort" is executed by asserting
    the STOP# line after it has claimed the cycle by asserting
    DEVSEL#.

    A "master abort" is executed by the master asseting (for at least
    one CLK period if not already asserted) and subsequently
    deasserting IDRY#; FRAME# is deasserted for at least one CLK
    period when IRDY# is asserted; the master abort is finally
    completed with deassertion of FRAME# and IRDY# lines.

  The "last data phase" is indicated when IRDY# is asserted, FRAME# is
  deasserted and either TRDY# or STOP# is asserted.

  A "data phase" completes when IRDY# is asserted with either STOP# or
  ir TRDY# asserted simultaneously.

  The initial data phase is marked by FRAME# fall; subsequent data
  phases are indicated by FRAME#, IRDY# and TRDY# all being asserted.