Subject: Questions regarding bound/unbound vunits
From: Avigail Orni (ORNIA@il.ibm.com)
Date: Tue Jan 20 2004 - 06:54:30 PST
Hi all,
In the last extensions meeting we discussed the question of vunits with no
binding.
The LRM states in section 7.2:
"If the Hierarchical_HDL_Name is not present, then the verification unit
binds to the top-level
module of the design under verification."
This may not be well-defined if there is more than one top-level vunit, and
therefore it was
decided that the default module for binding unbound vunits would be decided
by the tool.
I have two related questions:
(1)
Suppose the tool's default module for unbound vunits is M. Suppose signal A
is mentioned in an unbound vunit.
Is it correct to write M.A in the vunit, or should we write only A?
(2)
The following example is taken from section 7.2.1:
vunit ex1a(top_block.i1.i2) {
assert never (ena && enb);
}
The question is, where do we start looking for top_block.i1.i2 ?
Relative to what module should it be written? Should it be the tool's
"default top-level module",
or something else?
Regards,
Avigail
________________________________________________________
Avigail Orni
Formal Methods Group
IBM Haifa Research Laboratory
Tel: 972-4-829-6396 ornia@il.ibm.com
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