Subject: PSL 1.x LRM: Proposal: Default abort construct
From: VhdlCohen@aol.com
Date: Sat Jun 21 2003 - 19:20:19 PDT
Problem: Many designs use a global reset signal to reset the registers of a
design.
In PSL, there in no default abort like the default clock. Thus, in temporal
layers constructs, it becomes necessary to add at the end of each property the
statement
"abort reset_n==1'b0". For example:
property X =
always(({a;b;c} |=> {d; e; f}) abort reset_n==1'b0) ;
That task can be very cumbersome when dealing with many many assertions.
Solution: Define a default abort similar to the default clock. An explicit
abort overrides any default abort. A new default abort overrides a previously
declared default abort. Thus,
default abort = reset_n==1'b0;
property X =
always({a;b;c} |=> {d; e; f});
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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