Subject: Linking vunits to hardware design
From: Adriana Maggiore (adriana.maggiore@transeda.com)
Date: Thu Jun 27 2002 - 05:54:37 PDT
Dear all,
I have a few questions regarding the linking of a verification unit to
a hardware design.
Is it possible to have hierarchical HDL names in a vunit
linked to a module or an instance?
For example:
vunit V(module1)
{
assert always (instance1.req -> next! instance2.ack);
}
req -> module1.instance1.req
ack -> module1.instance2.ack
If yes, can the hierarchical HDL name reference a module?
(I think this should not be allowed)
For example:
vunit V(module1)
{
assert always (module2.req -> next! module2.ack);
}
In a vunit which is not linked to a design, is it possible
to use hierarchical HDL names which refer to different top level
modules? (I think this should not be allowed)
For example:
vunit V()
{
assert always (module1.req -> next! module2.ack);
}
Can vunits in an inheritance relationship be linked to different
top level modules?
For example
vunit A (mod1)
{
sequence S := {x; y};
}
vunit B (mod2)
{
inherit A;
cover {a; S; b}
}
the sequence to cover would be
{mod2.a; mod1.x; mod1.y; mod2.b}
Is this allowed?
I could not find explicit answers in the section "Linking a verification
unit to a hardware design"; should this section be extended with more
examples of allowed/disallowed cases?
Best regards,
Adriana
-- Adriana Maggiore TransEDA Tel: +44 (0)23 80 683523 4th floor, Black Horse House Fax: +44 (0)23 80 650805 Leigh Road, Eastleigh adriana.maggiore@transeda.com Hampshire, SO50 9FH, UK
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