Portable Stimulus Specification Working Group


The Accellera board recently approved the formation of a Working Group to define a Portable Test and Stimulus Specification.

Chair: Faris Khundakjie, Intel
Vice Chair: Tom Fitzpatrick, Mentor Graphics
Secretary: Tom Anderson, Cadence


Currently there is no single standard way to specify intent and behaviors that is reusable across target platforms (e.g., emulation, silicon, simulation, etc.). With this proposed standard, user companies will be able to specify the behaviors once, from which multiple implementations may be derived.

With a single specification, user companies will be able to select the best tool(s) from competing vendors to achieve the best results for their desired target platform.

Initial scope for the WG will be to define a portable test and stimulus specification language that can be used to generate stimulus for multiple target implementations.


In functional verification, several different languages and techniques are used to generate verification stimulus depending on whether a block, subsystem, SoC or system is being verified. When verifying RTL block and subsystem, SystemVerilog is frequently used though ‘e’, SystemC and VHDL are also used. At SoC and system level, embedded software is frequently used to exercise the design. Several challenges result from different languages and techniques being used for block- and subsystem-level verification. It is difficult to leverage block- or subsystem-level test scenarios at SoC and system level. In addition, the embedded software that drives stimulus in SoC and system level environments do not provide support for automated stimulus generation the way that languages such as SystemVerilog do (e.g., constrained random generation) in block- and subsystem-level environments.

The Portable Stimulus Working Group will create a standard in the area of enabling verification stimulus to be captured in such a manner that enables stimulus generation automation, and enables the same specification to be reused in multiple verification languages and contexts.

Join this Working Group

If you are an Accellera member and wish to participate in the PS-WG, please subscribe in the working group area (login required).


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